Z8F0213HH005EG Zilog, Z8F0213HH005EG Datasheet - Page 92

• Manufacturer Part Number: Z8F0213HH005EG
• Description: IC ENCORE MCU FLASH 2K 20SSOP
• Manufacturer: Zilog
• Series: Encore!® XP®r

Specifications of Z8F0213HH005EG

• Core Processor: Z8
• Core Size: 8-Bit
• Speed: 5MHz
• Connectivity: IrDA, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 2KB (2K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 105°C
• Package / Case: 20-SSOP
• For Use With: 770-1002 - ISP 4PORT ZILOG Z8 ENCORE! MCU269-4643 - KIT DEV Z8 ENCORE XP 28-PIN269-4630 - DEV KIT FOR Z8 ENCORE 8K/4K269-4629 - KIT DEV Z8 ENCORE XP 28-PIN269-4628 - KIT DEV Z8 ENCORE XP 8-PIN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Other names: 269-4044; Z8F0213HH005EG

Table 54. Timer 0–1 PWM Low Byte Register (TxPWML)
Table 55. Timer 0–1 Control Register 0 (TxCTL0)
BITS
FIELD
RESET
R/W
ADDR
BITS
FIELD
RESET
R/W
ADDR
PS024314-0308
Timer 0–1 Control Registers
TMODEHI
R/W
R/W
7
0
7
0
PWMH and PWML—Pulse-Width Modulator High and Low Bytes
These two bytes, {PWMH[7:0], PWML[7:0]}, form a 16-bit value that is compared to the
current 16-bit timer count. When a match occurs, the PWM output changes state. The
PWM output value is set by the TPOL bit in the Timer Control Register (TxCTL1)
register.
The TxPWMH and TxPWML registers also store the 16-bit captured timer value when
operating in CAPTURE or CAPTURE/COMPARE modes.
Time 0–1 Control Register 0
The Timer Control Register 0 (TxCTL0) and Timer Control Register 1 (TxCTL1)
determine the timer operating mode. It also includes a programmable PWM deadband
delay, two bits to configure timer interrupt definition, and a status bit to identify if the
most recent timer interrupt is caused by an input Capture event.
TMODEHI—Timer Mode High Bit
This bit along with the TMODE field in TxCTL1 register determines the operating mode
of the timer. This is the most-significant bit of the Timer mode selection value. See the
TxCTL1 register description for more details.
TICONFIG—Timer Interrupt Configuration
This field configures timer interrupt definition.
R/W
R/W
6
0
6
0
TICONFIG
R/W
R/W
5
0
5
0
Reserved
R/W
R/W
4
0
4
0
F05H, F0DH
F06H, F0EH
PWML
R/W
R/W
3
0
3
0
Z8 Encore! XP
PWMD
R/W
R/W
2
0
2
0
Product Specification
R/W
R/W
1
0
1
0
®
F0823 Series
INPCAP
R/W
R/W
0
0
0
0
Timers
82