ST72F325K4T6 STMicroelectronics, ST72F325K4T6 Datasheet - Page 73

• Manufacturer Part Number: ST72F325K4T6
• Description: MCU 8BIT 16KB FLASH/ROM 32-LQFP
• Manufacturer: STMicroelectronics
• Series: ST7r

Specifications of ST72F325K4T6

• Core Processor: ST7
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: I²C, SCI, SPI
• Peripherals: LVD, POR, PWM, WDT
• Number Of I /o: 24
• Program Memory Size: 16KB (16K x 8)
• Program Memory Type: FLASH
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 3.8 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 32-LQFP
• Processor Series: ST72F3x
• Core: ST7
• Data Bus Width: 8 bit
• Data Ram Size: 512 B
• Interface Type: I2C, SCI, SPI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 48
• Number Of Timers: 2
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: ST7232X-EVAL, ST7232X-SK/RAIS, ST72325-D/RAIS, ST7MDT20-DVP3, ST7MDT20J-EMU3, ST7MDT20M-EMU3, STX-RLINK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• For Use With: 497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 497-5605

10.4 16-BIT TIMER
10.4.1 Introduction
The timer consists of a 16-bit free-running counter
driven by a programmable prescaler.
It may be used for a variety of purposes, including
pulse length measurement of up to two input sig-
nals (input capture) or generation of up to two out-
put waveforms (output compare and PWM).
Pulse lengths and waveform periods can be mod-
ulated from a few microseconds to several milli-
seconds using the timer prescaler and the CPU
clock prescaler.
Some ST7 devices have two on-chip 16-bit timers.
They are completely independent, and do not
share any resources. They are synchronized after
a MCU reset as long as the timer clock frequen-
cies are not modified.
This description covers one or two 16-bit timers. In
ST7 devices with two timers, register names are
prefixed with TA (Timer A) or TB (Timer B).
10.4.2 Main Features
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The Block Diagram is shown in
*Note: Some timer pins may not be available (not
bonded) in some ST7 devices. Refer to the device
pin out description.
– 2 dedicated 16-bit registers
– 2 dedicated programmable signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
– 2 dedicated 16-bit registers
– 2 dedicated active edge selection signals
– 2 dedicated status flags
– 1 dedicated maskable interrupt
Programmable prescaler: f
Overflow status flag and maskable interrupt
External clock input (must be at least four times
slower than the CPU clock speed) with the choice
of active edge
1 or 2 Output Compare functions each with:
1 or 2 Input Capture functions each with:
Pulse width modulation mode (PWM)
One Pulse mode
Reduced Power Mode
5 alternate functions on I/O ports (ICAP1, ICAP2,
OCMP1, OCMP2, EXTCLK)*
CPU
Figure
divided by 2, 4 or 8
1.
When reading an input signal on a non-bonded
pin, the value will always be ‘1’.
10.4.3 Functional Description
10.4.3.1 Counter
The main block of the Programmable Timer is a
16-bit free running upcounter and its associated
16-bit registers. The 16-bit registers are made up
of two 8-bit registers called high and low.
Counter Register (CR):
Alternate Counter Register (ACR)
These two read-only 16-bit registers contain the
same value but with the difference that reading the
ACLR register does not clear the TOF bit (Timer
overflow flag), located in the Status register, (SR),
(see note at the end of paragraph titled 16-bit read
sequence).
Writing in the CLR register or ACLR register resets
the free running counter to the FFFCh value.
Both counters have a reset value of FFFCh (this is
the only value which is reloaded in the 16-bit tim-
er). The reset value of both counters is also
FFFCh in One Pulse mode and PWM mode.
The timer clock depends on the clock control bits
of the CR2 register, as illustrated in
value in the counter register repeats every
131072, 262144 or 524288 CPU clock cycles de-
pending on the CC[1:0] bits.
The timer frequency can be f
or an external frequency.
– Counter High Register (CHR) is the most sig-
– Counter Low Register (CLR) is the least sig-
– Alternate Counter High Register (ACHR) is the
– Alternate Counter Low Register (ACLR) is the
nificant byte (MS Byte).
nificant byte (LS Byte).
m ost significant byte (MS Byte).
least significant byte (LS Byte ).
CPU
/2, f
CPU
ST72325xx
Table
/4, f
1. The
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CPU
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