ST72F321BR9T6 STMicroelectronics, ST72F321BR9T6 Datasheet - Page 101

MCU 8BIT 60KB FLASH/ROM 64-LQFP

ST72F321BR9T6

Manufacturer Part Number
ST72F321BR9T6
Description
MCU 8BIT 60KB FLASH/ROM 64-LQFP
Manufacturer
STMicroelectronics
Series
ST7r
Datasheet

Specifications of ST72F321BR9T6

Core Processor
ST7
Core Size
8-Bit
Speed
8MHz
Connectivity
I²C, SCI, SPI
Peripherals
LVD, POR, PWM, WDT
Number Of I /o
48
Program Memory Size
60KB (60K x 8)
Program Memory Type
FLASH
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
3.8 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-LQFP
Processor Series
ST72F3x
Core
ST7
Data Bus Width
8 bit
Data Ram Size
2 KB
Interface Type
I2C, SCI, SPI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
48
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Development Tools By Supplier
ST7232X-EVAL, ST7232X-SK/RAIS, ST72321B-D/RAIS, ST7MDT20-DVP3, STX-RLINK
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 16 Channel
Cpu Family
ST7
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
2KB
# I/os (max)
48
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
3.8V
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
LQFP
For Use With
497-5046 - KIT TOOL FOR ST7/UPSD/STR7 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Lead Free Status / Rohs Status
 Details
Other names
497-5586

Available stocks

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Quantity
Price
Part Number:
ST72F321BR9T6
Quantity:
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Part Number:
ST72F321BR9T6
Manufacturer:
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Quantity:
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0
SERIAL COMMUNICATIONS INTERFACE (Cont’d)
10.6.4 Functional Description
The block diagram of the Serial Control Interface,
is shown in
isters:
– Two control registers (SCICR1 & SCICR2)
– A status register (SCISR)
– A baud rate register (SCIBRR)
– An extended prescaler receiver register (SCIER-
– An extended prescaler transmitter register (SCI-
Refer to the register descriptions in
for the definitions of each bit.
Figure 62. Word Length Programming
PR)
ETPR)
9-bit Word length (M bit is set)
Start
Figure 1.
Bit
8-bit Word length (M bit is reset)
Start
Bit
Bit0
Bit0
It contains six dedicated reg-
Bit1
Bit1
Data Frame
Idle Frame
Break Frame
Data Frame
Idle Frame
Break Frame
Bit2
Bit2
Section 0.1.7
Bit3
ST72321BRx, ST72321BARx ST72321BJx, ST72321BKx
Bit3
Bit4
Bit4
Bit5
Bit5
10.6.4.1 Serial Data Format
Word length may be selected as being either 8 or 9
bits by programming the M bit in the SCICR1 reg-
ister (see
The TDO pin is in low state during the start bit.
The TDO pin is in high state during the stop bit.
An Idle character is interpreted as an entire frame
of “1”s followed by the start bit of the next frame
which contains data.
A Break character is interpreted on receiving “0”s
for some multiple of the frame period. At the end of
the last break frame the transmitter inserts an ex-
tra “1” bit to acknowledge the start bit.
Transmission and reception are driven by their
own baud rate generator.
Bit6
Bit6
Possible
Bit7
Parity
Figure
Bit7
Bit
Possible
Parity
Bit8
Bit
Stop
Bit
1.).
Stop
Bit
Extra
Start
Next
Start
Bit
Bit
‘1’
Extra
Next Data Frame
Next
Start
Start
Bit
Bit
‘1’
Start
Bit
Next Data Frame
Start
Bit
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