MC9RS08KA2CDB Freescale Semiconductor, MC9RS08KA2CDB Datasheet
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MC9RS08KA2CDB
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MC9RS08KA2 MC9RS08KA1 Data Sheet RS08 Microcontrollers MC9RS08KA2 Rev. 4 12/2008 freescale.com ...
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MC9RS08KA2 Features 8-Bit RS08 Central Processor Unit (CPU) • Simplified S08 instruction set with added high-performance instructions — LDA, STA, and CLR instructions support the short addressing mode; address $0000 to $001F can be accessed via a single-byte instruction — ...
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... MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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MC9RS08KA2 Series Data Sheet Covers: MC9RS08KA2 MC9RS08KA1 MC9RS08KA2 Rev. 4 12/2008 ...
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... Revised 4 12/2008 Changed the mechanical drawing of 6-pin DFN in the Information and Mechanical This product incorporates SuperFlash Freescale‚ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. © Freescale Semiconductor, Inc., 2006-2008. All rights reserved. 6 Description of Changes ir_wu Figure 1-2. Updated “How to Reach Us” information. ...
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... Central Processor Unit (RS08CPUV1) ........................................... 57 Chapter 9 Internal Clock Source (RS08ICSV1)............................................... 75 Chapter 10 Analog Comparator (RS08ACMPV1).............................................. 83 Chapter 11 Modulo Timer (RS08MTIMV1) ......................................................... 89 Chapter 12 Development Support ..................................................................... 97 Appendix A Electrical Characteristics.............................................................. 109 Appendix B Ordering Information and Mechanical Drawings........................ 123 Freescale Semiconductor List of Chapters Title MC9RS08KA2 Series Data Sheet, Rev. 4 Page 7 ...
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... RAM and Register Addresses and Bit Assignments .......................................................................27 4.5 RAM ................................................................................................................................................29 4.6 Flash ................................................................................................................................................29 4.6.1 Features ...........................................................................................................................29 4.6.2 Flash Programming Procedure .......................................................................................30 4.6.3 Flash Mass Erase Operation ...........................................................................................30 Freescale Semiconductor Table of Contents Title Chapter 1 Chapter 2 Pins and Connections PP ........................................................................................................ 19 Chapter 3 Modes of Operation Chapter 4 Memory MC9RS08KA2 Series Data Sheet, Rev. 4 ...
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... Output Slew Rate Control Enable ...................................................................48 Keyboard Interrupt (RS08KBIV1) 7.1 Introduction .....................................................................................................................................51 7.1.1 Features ...........................................................................................................................51 7.1.2 Modes of Operation ........................................................................................................52 7.1.2.1 Operation in Wait Mode ..................................................................................52 7.1.2.2 Operation in Stop Mode ..................................................................................52 7.1.2.3 Operation in Active Background Mode ..........................................................52 10 Title Chapter 5 Chapter 6 Parallel Input/Output Control Chapter 7 MC9RS08KA2 Series Data Sheet, Rev. 4 Page Freescale Semiconductor ...
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... Extended Addressing Mode (EXT) ................................................................................63 8.3.8 Indexed Addressing Mode (IX, Implemented by Pseudo Instructions) .........................63 8.4 Special Operations ...........................................................................................................................63 8.4.1 Reset Sequence ...............................................................................................................64 8.4.2 Interrupts .........................................................................................................................64 8.4.3 Wait and Stop Mode .......................................................................................................64 8.4.4 Active Background Mode ...............................................................................................64 8.5 Summary Instruction Table .............................................................................................................65 Freescale Semiconductor Title Chapter 8 MC9RS08KA2 Series Data Sheet, Rev. 4 Page 11 ...
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... Operation in Stop Mode ..................................................................................84 10.1.2.3 Operation in Active Background Mode ..........................................................84 10.1.3 Block Diagram ................................................................................................................84 10.2 External Signal Description ............................................................................................................86 10.3 Register Definition ..........................................................................................................................86 10.3.1 ACMP Status and Control Register (ACMPSC) ............................................................86 10.4 Functional Description ....................................................................................................................87 12 Title Chapter 9 Chapter 10 MC9RS08KA2 Series Data Sheet, Rev. 4 Page Freescale Semiconductor ...
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... BDC Registers and Control Bits ...................................................................................................103 12.4.1 BDC Status and Control Register (BDCSCR) .............................................................103 12.4.2 BDC Breakpoint Match Register ..................................................................................104 12.5 RS08 BDC Commands ..................................................................................................................105 Freescale Semiconductor Title Chapter 11 Modulo Timer (RS08MTIMV1) Chapter 12 Development Support MC9RS08KA2 Series Data Sheet, Rev. 4 ...
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... A.8 Internal Clock Source Characteristics ...........................................................................................117 A.9 AC Characteristics .........................................................................................................................118 A.9.1 Control Timing ...............................................................................................................118 A.10 FLASH Specifications ...................................................................................................................119 Ordering Information and Mechanical Drawings B.1 Ordering Information ....................................................................................................................123 B.2 Mechanical Drawings ....................................................................................................................123 14 Title Appendix A Electrical Characteristics Appendix B MC9RS08KA2 Series Data Sheet, Rev. 4 Page Freescale Semiconductor ...
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... USER RAM — 63 BYTES INTERNAL CLOCK SOURCE (ICS POWER AND V INTERNAL REGULATOR DD Figure 1-1. MC9RS08KA2 Series Block Diagram Freescale Semiconductor 5-BIT KEYBOARD INTERRUPT MODULE (KBI) ANALOG COMPARATOR MODULE (ACMP) MODULO TIMER MODULE (MTIM) NOTES: (1) Pins are software configurable with pullup/pulldown device if input port. ...
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... ICS output frequency and is used by all of the internal modules. 16 Table 1-1. Block Versions Module SYSTEM CONTROL LOGIC RTICLKS 1-kHz RTI ÷32 FIXED CLOCK (XCLK) ÷2 SYNC BUS CLOCK ÷2 COP MC9RS08KA2 Series Data Sheet, Rev. 4 Version TCLK MTIM CPU FLASH BDC BDC BDC Freescale Semiconductor ...
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... Device Pin Assignment Figure 2-1 and Figure 2-3 show the pin assignments in the packages available for the MC9RS08KA2 Series. PTA2/KBIP2/TCLK/RESET/V PTA3/ACMPO/BKGD/MS Figure 2-1. MC9RS08KA2 Series in 6-Pin DFN PTA2/KBIP2/TCLK/RESET/V PTA3/ACMPO/BKGD/MS Figure 2-2. MC9RS08KA2 Series in 8-Pin PDIP Freescale Semiconductor ...
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... This pin is not available in the 6-pin package. Figure 2-4. Reference System Connection Diagram 2.4 Pin Detail This section provides a detailed description of system connections MC9RS08KA2 BUK 0.1 μF 10 μ PTA0/KBIP0/ACMP+ PTA1/KBIP1/ACMP- PTA4/KBIP4 (Note 1) PTA5/KBIP5 (Note 1) MC9RS08KA2 Series Data Sheet, Rev. 4 PTA0/KBIP0/ACMP+ 8 PTA1/KBIP1/ACMP- 7 PTA4/KBIP4 6 PTA5/KBIP5 5 BKGD/MS RESET/V PP Freescale Semiconductor ...
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... Although the BKGD pin is a pseudo open-drain pin, the background debug communication protocol provides brief, actively driven, high speedup pulses to ensure fast rise times. Small capacitances from Freescale Semiconductor PP Section A.10, “FLASH Specifications”) is required on this pin ...
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... Analog comparator output BKGD Background debug data MS Mode select SWC PTA4 General-purpose input/output (GPIO) KBIP4 Keyboard interrupt (stop/wait wakeup only) SWC PTA5 General-purpose input/output (GPIO) KBIP5 Keyboard interrupt (stop/wait wakeup only) MC9RS08KA2 Series Data Sheet, Rev Alternative Functions Power Ground is attached, PP Freescale Semiconductor ...
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... Active background mode is entered in any of four ways: • When the BKGD/MS pin is low during power-on-reset (POR) or immediately after issuing a background debug force reset (BDC_RESET) command • When a BACKGROUND command is received through the BKGD pin • When a BGND instruction is executed Freescale Semiconductor MC9RS08KA2 Series Data Sheet, Rev ...
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... MCU is operated in run mode for the first time. When the MC9RS08KA2 Series is shipped from the Freescale Semiconductor factory, the Flash program memory is usually erased so there is no program that could be executed in run mode until the Flash memory is initially programmed. The active background mode can also be used to erase and reprogram the Flash memory after it has been previously programmed ...
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... MCU from stop. The trimmed 32-kHz clock in the ICS module can also be enabled for the real-time interrupt to allow a wakeup from stop mode with no external components. The 32-kHz clock reference is enabled by setting Freescale Semiconductor Table 3-1. Wait Mode Behavior Digital ...
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... If ENBDM is set when the CPU Digital ICS ACMP Standby On Optionally on Table 3-4. LVD Enabled Stop Mode Behavior Digital ICS ACMP Standby Optionally Optionally on on MC9RS08KA2 Series Data Sheet, Rev. 4 Regulator I/O Pins RTI On States held Optionally on Regulator I/O Pins RTI On States held Optionally on Freescale Semiconductor ...
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... Other peripheral registers ($0200–$023F) • Nonvolatile memory — MC9RS08KA2: $3800–$3FFF — MC9RS08KA1: $3C00—$3FFF 1. Physical RAM in $000E can be accessed through the D[X] register when the content of the index register X is $0E. Freescale Semiconductor MC9RS08KA2 Series Data Sheet, Rev ...
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... HIGH PAGE REGISTERS $023F $E0 $3C00 $3FFB $3FFC $3FFD $3FFF MC9RS08KA2 Series Data Sheet, Rev. 4 PAGE REGISTER CONTENT $00 FAST ACCESS RAM 14 BYTES D[X] REGISTER X PAGESEL RAM 48 BYTES UNIMPLEMENTED PAGING WINDOW UNIMPLEMENTED $08 (reset value) UNIMPLEMENTED $F0 FLASH 1020 BYTES NVOPT FLASH MC9RS08KA1 Freescale Semiconductor ...
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... The fast access RAM area can be accessed by instructions using tiny, short, and direct addressing mode instructions. For tiny addressing mode instructions, the operand is encoded along with the opcode to a single byte. Freescale Semiconductor D[X] Register X Content of this location can be accessed via D[X] Figure 4-2 ...
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... ILAD 0 LVD 0 0 BKGDPE ACMP MTIM RTI — — — — — — RTIS LVDSE LVDE — — — — Freescale Semiconductor 1 Bit 0 1 Bit 0 1 Bit 0 PTAD0 PTADD0 — — ACMOD 0 IREFSTEN FTRIM 0 0 KBIMOD KBIPE0 KBEDG0 AD6 — — ...
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... Flash memory after final assembly of the application product possible to program the entire array through the single-wire background debug interface. Because the device does not include on-chip charge pump circuitry, external V 4.6.1 Features Features of the Flash memory include: Freescale Semiconductor Table 4-1. Register Summary (continued — ...
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... These operations must be performed in the order shown; other unrelated operations may occur between the steps. 4.6.3 Flash Mass Erase Operation Use the following procedure to mass erase the entire Flash memory: 1. Apply external Set the MASS bit in the Flash control register. 30 NOTE MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... Security can always be disengaged through the background debug interface by following these steps: 1. Mass erase Flash via background BDM commands or RAM loaded program. 2. Perform reset and the device will boot up with security disengaged. Freescale Semiconductor NOTE Operation,” via BDM commands. MC9RS08KA2 Series Data Sheet, Rev. 4 ...
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... Flash memory cannot be accessed by instructions from any unsecured source including the background debug interface; refer to 0 Security engaged. 1 Security disengaged. 32 NOTE Figure 4-3. Flash Options Register (FOPT) Table 4-2. FOPT Field Descriptions Description Section 4.6.4, “Security”. MC9RS08KA2 Series Data Sheet, Rev Freescale Semiconductor 0 SECD ...
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... Reset 0 0 Field 7:0 Page Selector— These bits define the address line bit 6 to bit 13, which determines the 64-byte block boundary AD[13:6] of the memory block accessed via the direct page window. See Freescale Semiconductor HVEN 0 0 Figure 4-4. Flash Control Register (FLCR) Table 4-3 ...
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... AD[13:6] Table 4-5. Paging Window for $00C0–$00FF Page Memory Address $00 $0000–$003F $01 $0040–$007F $02 $0080–$00BF $03 $00C0–$00FF $04 $0100–$013F . . . . . . $FE $3F80–$3FBF $FF $3FC0–$3FFF NOTE MC9RS08KA2 Series Data Sheet, Rev Freescale Semiconductor ...
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... On-chip peripheral modules are disabled and I/O pins are initially configured as general-purpose high-impedance inputs with pullup/pulldown devices disabled. The MC9RS08KA2 Series has seven sources for reset: • External pin reset (PIN) — enabled using RSTPE in SOPT • Power-on reset (POR) • Low-voltage detect (LVD) Freescale Semiconductor MC9RS08KA2 Series Data Sheet, Rev ...
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... COP Overflow Count cycles (32 ms cycles (256 ms) Values shown in this column are based on ≈ 1 ms. See the Section A.9.1, “Control RTI RTI Timing,” for the tolerance of this value. MC9RS08KA2 Series Data Sheet, Rev. 4 Section 5.8.2, Table 5-1 summaries the 1 Freescale Semiconductor ...
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... ICS module. The 32-kHz internal clock reference is divided the RTI logic to produce a trimmed 1-kHz clock Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control level. Both the POR bit and the LVD bit in SRS are set LVD ...
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... Section 5.8.4, “System Real-Time Interrupt Status and Chapter 4, “Memory,” for the absolute address assignments 5 4 COP ILOP ILAD Writing any value to SRS address clears COP watchdog timer Note 1 Note 1 Note 1 Figure 5-1. System Reset Status (SRS) MC9RS08KA2 Series Data Sheet, Rev. 4 Chapter 3, “Modes LVD Freescale Semiconductor ...
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... BKGDPE is reset Flash security is engaged (SECD = 0). When the device is reset into active BDM mode (MS is low during reset), BKGDPE is always reset to 1 such that BDM communication is allowed. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Table 5-2. SRS Field Descriptions ...
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... The revision number that is hard coded into these bits reflects the current silicon revision level. Figure 5-3. System Device Identification Register — High (SDIDH) 40 Table 5-3. SOPT Register Field Descriptions Description pin functions as PTA2/KBIP2/TCLK/V PP pin functions as RESET REV1 REV0 ID11 0 (Note 1) 0 (Note 1) MC9RS08KA2 Series Data Sheet, Rev. 4 pin to function ID10 ID9 Freescale Semiconductor 0 ID8 0 ...
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... Real-time interrupt request clock source is internal 1-kHz oscillator. 1 Real-time interrupt request clock source is internal trimmed 32-kHz oscillator (ICS module) and is divided RTI logic to produce a trimmed 1-kHz clock source for RTI counter. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control Description ...
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... RTIS bits must be selected to %000 and RTICLKS bit must be set Description Table 5-7. Real-Time Interrupt Period RTI Timeout Disable RTI 128 ms 256 ms 512 ms 1.024 s RTI (Table A-7). NOTE MC9RS08KA2 Series Data Sheet, Rev. 4 Table 5-7. 1 (Table A-8) and the Freescale Semiconductor ...
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... LVD logic enabled. 0 Bandgap Buffer Enable — This bit enables an internal buffer for the bandgap voltage reference for use by the BGBE ACMP module on one of its internal channels. 0 Bandgap buffer disabled. 1 Bandgap buffer enabled. Freescale Semiconductor Chapter 5 Resets, Interrupts, and General System Control (1) LVDIE ...
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... There is no pending LVD interrupt; i.e., LVDF flag and/or LVDE bit is cleared. 1 There is a pending LVD interrupt; i.e., LVDF flag, LVDIE, and LVDE bits are set KBI ACMP 0 0 Table 5-9. SIP1 Register Field Descriptions Description MC9RS08KA2 Series Data Sheet, Rev MTIM RTI Freescale Semiconductor 0 LVD 0 ...
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... The data direction control bit (PTADDn) determines whether the output buffer for the associated pin is enabled, and also controls the source for port data register reads. The input buffer for the associated pin is always enabled unless the pin is enabled as an analog function output-only pin. Freescale Semiconductor Figure PTADDn ...
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... Refer to tables in Chapter 4, “Memory,” for the absolute address assignments for all parallel I/O. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 6.2.1 Port A Registers Port A parallel I/O function is controlled by the data and data direction registers described in this section ...
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... Refer to tables in Chapter 4, “Memory,” for the absolute address assignments of the pin control registers. This section refers to registers and control bits only by their names. A Freescale Semiconductor-provided equate or header file normally is used to translate these names into the appropriate absolute addresses. 6.3.1 Port A Pin Control Registers The pins associated with port A are controlled by the registers provided in this section ...
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... When enabled, slew control limits the rate at which an output can transition in order to reduce EMC emissions. Slew rate control has no effect on pins that are configured as inputs PTAPE5 PTAPE4 Description PTAPUD5 PTAPUD4 Description MC9RS08KA2 Series Data Sheet, Rev PTAPE2 PTAPE1 PTAPE0 PTAPUD2 PTAPUD1 PTAPUD0 Freescale Semiconductor ...
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... PTASE[5:3;1:0] rate control is enabled for the associated PTA pin. For port A pins that are configured as inputs, these bits have no effect. 0 Output slew rate control disabled for port A bit n. 1 Output slew rate control enabled for port A bit n. Freescale Semiconductor PTASE5 PTASE4 ...
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... Chapter 6 Parallel Input/Output Control 50 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... Each keyboard interrupt pin is programmable as falling edge (or rising edge) only, or both falling edge and low level (or both rising edge and high level) interrupt sensitivity • One software-enabled keyboard interrupt • Exit from low-power modes Freescale Semiconductor 5-BIT KEYBOARD INTERRUPT MODULE (KBI) ANALOG COMPARATOR MODULE ...
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... The signal properties of KBI are shown in Signal KBIPn 52 Figure V DD CLR KEYBOARD INTERRUPT FF KBMOD Table 7-1. Table 7-1. Signal Properties Function Keyboard interrupt pins MC9RS08KA2 Series Data Sheet, Rev. 4 7-2. BUSCLK KBACK RESET KBF SYNCHRONIZER STOP BYPASS KBI STOP INTERRUPT REQUES KBIE I/O I Freescale Semiconductor T ...
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... Keyboard Interrupt Flag — KBF indicates that a keyboard interrupt is detected. Writes have no effect on KBF. KBF 0 No keyboard interrupt detected. 1 Keyboard interrupt detected. 2 Keyboard Acknowledge — Writing KBACK is part of the flag-clearing mechanism. KBACK always reads KBACK as 0. Freescale Semiconductor Chapter 4, “Memory,” for the absolute address assignments Table 7-2. Table 7-2. KBI Register Summary 7 6 ...
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... Falling edge/low level. 1 Rising edge/high level. 54 Description 5 4 KBIPE5 KBIPE4 0 0 Figure 7-4. KBI Pin Enable Register (KBIPE) Description 5 4 KBEDG5 KBEDG4 0 0 Description MC9RS08KA2 Series Data Sheet, Rev KBIPE2 KBIPE1 KBIPE0 KBEDG2 KBEDG1 KBEDG0 Freescale Semiconductor ...
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... If using internal pullup/pulldown device, configure the associated I/O port pullup/pulldown device. 3. Enable the KBI polarity by setting the appropriate KBEDGn bits in KBIES. 4. Enable the KBI pins by setting the appropriate KBIPEn bits in KBIPE. Freescale Semiconductor MC9RS08KA2 Series Data Sheet, Rev. 4 Chapter 7 Keyboard Interrupt (RS08KBIV1) ...
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... Chapter 7 Keyboard Interrupt (RS08KBIV1) 5. Write to KBACK in KBISC to clear any false interrupts. 6. Set KBIE in KBISC to enable interrupts. 56 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... This chapter is a summary of information about the registers, addressing modes, and instruction set of the RS08 Family CPU. For a more detailed discussion, refer to the RS08 Core Reference Manual, volume 1, Freescale Semiconductor document order number RS08RMv1. The RS08 CPU has been developed to target extremely low-cost embedded applications using a process-independent design methodology, allowing it to keep pace with rapid developments in silicon processing technology ...
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... SHADOW PROGRAM COUNTER CONDITION CODE REGISTER Z C CCR CARRY ZERO Figure 8-1. CPU Registers 7 0 INDEXED DATA REGISTER D[X] (location $000E INDEX REGISTER X (location $000F PAGE SELECT REG PAGESEL (location $001F) Figure 8-2. Memory Mapped Registers MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... blo lower ;branch if A smaller 5 more: deca ;do this if A not higher than or same as 5 lower: Freescale Semiconductor Figure 8-3. Condition Code Register (CCR) MC9RS08KA2 Series Data Sheet, Rev. 4 Chapter 8 Central Processor Unit (RS08CPUV1) Figure 8-3 identifies the CCR bits Z C ...
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... This 8-bit index register allows the user to index or address any location in the direct page address space. This register resides at the memory mapped location $000F. For details on the X register, please refer to Section 8.3.8, “Indexed Addressing Mode (IX, Implemented by Pseudo 60 MC9RS08KA2 Series Data Sheet, Rev. 4 Instructions).” Instructions).” Freescale Semiconductor ...
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... Relative Addressing Mode (REL) Relative addressing mode is used to specify the offset address for branch instructions relative to the program counter. Typically, the programmer specifies the destination with a program label or an Freescale Semiconductor MC9RS08KA2 Series Data Sheet, Rev. 4 Chapter 8 Central Processor Unit (RS08CPUV1) ...
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... Because the 4-bit address is embedded in the opcode, only the least significant four bits of the address must be included in the instruction; this saves program space and execution time. During execution, the CPU adds 10 high-order 0s to the 4-bit operand address and uses the combined 14-bit address ($000x) to access the intended operand. 62 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... CPU starts at the beginning of an application program after power is first applied. After the program begins running, the current instruction normally determines what the CPU will do next. Two exceptional events can cause the CPU to temporarily suspend normal program execution: Freescale Semiconductor MC9RS08KA2 Series Data Sheet, Rev. 4 Chapter 8 Central Processor Unit (RS08CPUV1) ...
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... Refer to the Development Support chapter for detailed information on active background mode. The arithmetic left shift pseudo instruction is also available because its operation is identical to logical shift left. 64 Resets and Interrupts MC9RS08KA2 Series Data Sheet, Rev. 4 chapter. Resets and Interrupts Freescale Semiconductor ...
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... CCR activity notation – = Bit not affected 0 = Bit forced Bit forced Bit set or cleared according to results of operation U = Undefined after the operation Machine coding notation Freescale Semiconductor MC9RS08KA2 Series Data Sheet, Rev. 4 Chapter 8 Central Processor Unit (RS08CPUV1) Table 8-1 through Table 8-2. 65 ...
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... Address modes INH = Inherent (no operands) IMD = Immediate to Direct (in MOV instruction) IMM = Immediate DD = Direct to Direct (in MOV instruction) DIR = Direct SRT = Short TNY = Tiny EXT = Extended REL = 8-bit relative offset 66 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... BGND Background 1. This is a pseudo instruction supported by the normal RS08 instruction set. 2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register. Freescale Semiconductor Operation A ← (A) + (M) + (C) A ← (A) + (X) + (C) A ← (A) + (M) A ← ...
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... REL 34 rr — — REL 35 rr — — REL 36 rr — — REL 30 rr — — REL 30 00 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 (b0 (b1 (b2 (b3 — IX (b4 (b5 (b6 (b7 DIR (b0 DIR (b1 DIR (b2 DIR (b3 DIR (b4 DIR (b5 DIR (b6 DIR (b7 Freescale Semiconductor ...
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... Set Bit n in Memory BSET n,X 1. This is a pseudo instruction supported by the normal RS08 instruction set. 2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register. Freescale Semiconductor Operation PC ← (PC) + $0003 + rel, if (Mn ← 1 MC9RS08KA2 Series Data Sheet, Rev ...
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... INH 43 DIR — — INH 4B rr INH DIR 3A dd TNY 5x — INH 4A DIR 5F IMM A8 ii DIR B8 dd — DIR B8 0F DIR 3C dd TNY 2x — INH 4C INH 2F — — EXT — — EXT IMM A6 ii DIR B6 dd — SRT Cx/ Freescale Semiconductor ...
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... STX opr8a Memory STOP Put MCU into stop mode 1. This is a pseudo instruction supported by the normal RS08 instruction set. 2. This instruction is different from that of the HC08 and HCS08 in that the RS08 does not auto-increment the index register. Freescale Semiconductor Operation $0F ← ( ...
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... A ← (A) – (M) A ← (A) – (X) X ← (A) (M) – $00 (A) – $00 (X) – $00 A ← (X) MC9RS08KA2 Series Data Sheet, Rev. 4 Effect on CCR Z C IMM A0 ii DIR B0 dd TNY DIR 7F — INH INH AA 00 — INH — INH CF — — INH AF Freescale Semiconductor ...
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... TNY 2 DIR 1 INH Inherent REL Relative IMM Immediate SRT Short DIR Direct TNY Tiny EXT Extended DD Direct-Direct IMD Immediate-Direct Gray box is decoded as illegal instruction Freescale Semiconductor Table 8-2. Opcode Map INH TNY TNY TNY SRT DEC ADD SUB CLR 1 TNY 1 TNY ...
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... Chapter 8 Central Processor Unit (RS08CPUV1) 74 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... MC9RS08KA1 — 1024 BYTES USER RAM — 63 BYTES INTERNAL CLOCK SOURCE (ICS POWER AND V INTERNAL REGULATOR DD Figure 9-1. MC9RS08KA2 Series Block Diagram Highlighting ICS Block Freescale Semiconductor 5-BIT KEYBOARD 5 INTERRUPT MODULE (KBI) ACMP+ ANALOG COMPARATOR ACMP- MODULE (ACMP) ACMPO MODULO TIMER ...
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... In stop mode, the FLL is disabled and the internal reference clocks can be selected to be enabled or disabled. The ICS does not provide an MCU clock source. 9.1.3 Block Diagram Figure 9-2 shows the ICS block diagram (FEI) l (FBI) l Low Power (FBILP) MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... Register Definition Table 9 summary of ICS registers. Name ICSC1 W R ICSC2 BDIV W R ICSTRM ICSSC W 9.3.1 ICS Control Register 1 (ICSC1) Freescale Semiconductor CLKS LP DCOOUT DCO ICSIRCLK 9 Filter FLL Table 9-1. ICS Register Summary CLKS 0 0 TRIM MC9RS08KA2 Series Data Sheet, Rev. 4 ...
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... FLL is disabled in bypass modes 0 FLL is not disabled in bypass mode Figure 9-3. ICS Control Register 1 (ICSC1) Table 9-2. ICSC1 Field Descriptions Description Figure 9-4. ICS Control Register 2 (ICSC2) Table 9-3. ICSC2 Field Descriptions Description MC9RS08KA2 Series Data Sheet, Rev IREFSTEN Freescale Semiconductor ...
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... Internal reference clock is selected 0 ICS Fine Trim — The FTRIM bit controls the smallest adjustment of the internal reference clock frequency. FTRIM Setting FTRIM will increase the period and clearing FTRIM will decrease the period by the smallest amount possible. Freescale Semiconductor TRIM 0 ...
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... In FLL bypassed internal low power mode, the ICSOUT clock is derived from the internal reference clock and the FLL is disabled. 80 CLKS=1 LP=0 FLL Bypassed Internal (FBI Stop Figure 9-7. Clock Switching Modes MC9RS08KA2 Series Data Sheet, Rev. 4 CLKS=1 LP=1 FLL Bypassed Internal Low Power(FBILP) Freescale Semiconductor ...
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... The user should trim the device to an allowable frequency before changing BDIV to a divide by 1 operation. Freescale Semiconductor , for the FLL to return its previous acquired fll_wu , before FLL will be guaranteed desired frequency ...
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... The ICS provides the ICSFFCLK output which can be used as an additional clock source to a peripheral such as a timer, when the ICS is in FEI. ICSFFCLK is not a valid clock source for a peripheral when in either FBI or FBILP modes. ICSFFCLK is ICSRCLK divided by two. 82 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... MC9RS08KA1 — 1024 BYTES USER RAM — 63 BYTES INTERNAL CLOCK SOURCE (ICS POWER AND V INTERNAL REGULATOR DD Figure 10-1. MC9RS08KA2 Series Block Diagram Highlighting ACMP Block and Pins Freescale Semiconductor 5-BIT KEYBOARD 5 INTERRUPT MODULE (KBI) ACMP+ ANALOG COMPARATOR ACMP- MODULE (ACMP) ACMPO MODULO TIMER ...
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... If stop is exited with a reset, the ACMP will be put into its reset state. 10.1.2.3 Operation in Active Background Mode When the MCU is in active background mode, the ACMP will continue to operate normally. 10.1.3 Block Diagram The block diagram for the analog comparator module is shown in 84 MC9RS08KA2 Series Data Sheet, Rev. 4 Figure 10-2. Freescale Semiconductor ...
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... Internal Bandgap Reference Voltage ACMP+ ACMP- Figure 10-2. Analog Comparator (ACMP) Block Diagram Freescale Semiconductor Internal Bus ACBGS Status and Control ACME Register ACO + Interrupt Control - Comparator MC9RS08KA2 Series Data Sheet, Rev. 4 Analog Comparator (RS08ACMPV1) ACMP INTERRUPT ACIE REQUEST ACF ACOPE ...
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... Figure 10-3. ACMP Status and Control Register (ACMPSC) 86 Table 10-1. Table 10-1. Signal Properties Function Inverting analog input to the ACMP (Minus input) Non-inverting analog input to the ACMP (Positive input) Digital output of the ACMP ACO ACF ACIE MC9RS08KA2 Series Data Sheet, Rev ACOPE ACMOD Freescale Semiconductor ...
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... ACF to be set. ACF can be set on a rising edge of the comparator output, a falling edge of the comparator output, or either a rising or a falling edge (toggle). The comparator output can be read directly through ACO. The comparator output can also be driven onto the ACMPO pin using ACOPE. Freescale Semiconductor Table 10-2. ACMPSC Field Descriptions Description MC9RS08KA2 Series Data Sheet, Rev ...
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... Maximum source impedence is restricted to the value specified in Table A-6. To achieve maximum performance device is recommended to enter WAIT/STOP mode for ACMP measurement and adjacent pin toggling must be avoided. 88 NOTE MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... MC9RS08KA1 — 1024 BYTES USER RAM — 63 BYTES INTERNAL CLOCK SOURCE (ICS POWER AND V INTERNAL REGULATOR DD Figure 11-1. MC9RS08KA2 Series Block Diagram Highlighting MTIM Block and Pin Freescale Semiconductor 5-BIT KEYBOARD 5 INTERRUPT MODULE (KBI) ACMP+ ANALOG COMPARATOR ACMP- MODULE (ACMP) ACMPO MODULO TIMER ...
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... The MTIM suspends all counting until the MCU returns to normal user operating mode. Counting resumes from the suspended value as long as an MTIM reset did not occur (TRST written any value is written to the MTIMMOD register). 90 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... An 8-bit modulo register Refer to the direct-page register summary in the memory section of this data sheet for the absolute address assignments for all MTIM registers. This section refers to registers and control bits only by their names. Freescale Semiconductor Figure PRESCALE AND CLOCK SELECT DIVIDE ...
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... TSTP is cleared. Reset sets TSTP to prevent the MTIM from counting. 0 MTIM counter is active. 1 MTIM counter is stopped. 92 Table 11-2. MTIM Register Summary TOF 0 TOIE TSTP TRST 0 0 CLKS TSTP TRST Table 11-3. MTIMSC Field Descriptions Description MC9RS08KA2 Series Data Sheet, Rev COUNT MOD Freescale Semiconductor ...
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... All other encodings default to MTIM clock source ÷ 256. 11.3.3 MTIM Counter Register (MTIMCNT) MTIMCNT is the read-only value of the current MTIM count of the 8-bit counter Reset Figure 11-5. MTIM Counter Register (MTIMCNT) Freescale Semiconductor CLKS Table 11-4. MTIMCLK Field Description Description 5 4 ...
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... MOD value of $00 puts the MTIM in free-running mode. Writing to MTIMMOD resets the COUNT to $00 and clears TOF. Reset sets the modulo to $00. 94 Table 11-5. MTIMCNT Field Description Description MOD Table 11-6. MTIMMOD Descriptions Description MC9RS08KA2 Series Data Sheet, Rev Freescale Semiconductor ...
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... The MTIM allows for an optional interrupt to be generated whenever TOF is set. To enable the MTIM overflow interrupt, set the MTIM overflow interrupt enable bit (TOIE) in MTIMSC. TOIE must never be written while TOF = 1. Instead, TOF must be cleared first, then the TOIE can be set to 1. Freescale Semiconductor MC9RS08KA2 Series Data Sheet, Rev. 4 Modulo Timer (RS08MTIMV1) ...
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... When the counter, MTIMCNT, reaches the modulo value of $AA, the counter overflows to $00 and continues counting. The timer overflow flag, TOF, sets when the counter value changes from $AA to $00. An MTIM overflow interrupt is generated when TOF is set, if TOIE = 1. 96 $A8 $A9 $AA $AA MC9RS08KA2 Series Data Sheet, Rev. 4 $00 $01 Freescale Semiconductor ...
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... Active background mode commands for CPU register access • GO and TRACE1 commands • BACKGROUND command can wake CPU from wait or stop modes Freescale Semiconductor COMMAND TRANSLATOR RS-232 USB, Ethernet RS08 POD MC9RS08KA2 Series Data Sheet, Rev. 4 HOST ...
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... The RS08 BDM pods supply the V The V connection from the pod is shared with RESET as shown in PP see the FLASH specifications in the electricals appendix. 98 voltage to the RS08 MCU when in-circuit programming is required. PP MC9RS08KA2 Series Data Sheet, Rev. 4 Figure 12-2. For V requirements PP Freescale Semiconductor ...
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... BDM. 12.3.2 Communication Details The BDC serial interface requires the host to generate a falling edge on the BKGD pin to indicate the start of each bit time. The host provides this falling edge whether data is transmitted or received. Freescale Semiconductor 2 GND BKGD 1 ...
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... The host must sample the bit level approximately 10 cycles after it started the bit time. 100 10 CYCLES TARGET SENSES BIT LEVEL MC9RS08KA2 Series Data Sheet, Rev. 4 EARLIEST START OF NEXT BIT Freescale Semiconductor ...
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... BKGD pin low for 13 BDC clock cycles, then briefly drives it high to speed up the rising edge. The host samples the bit level approximately 10 cycles after starting the bit time. Freescale Semiconductor HIGH IMPEDANCE R-C RISE ...
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... To send a logic 1, BKGD must be held low for at least four BDC cycles, be released by the eighth cycle, and be held high until at least the sixteenth BDC cycle. 102 HIGH IMPEDANCE 10 CYCLES 10 CYCLES HOST SAMPLES BKGD PIN MC9RS08KA2 Series Data Sheet, Rev. 4 SPEEDUP PULSE EARLIEST START OF NEXT BIT Freescale Semiconductor ...
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... BDM cannot be made active (non-intrusive commands still allowed). 1 BDM can be made active to allow active background mode commands. 6 Background Mode Active Status — This is a read-only status bit BDMACT 0 BDM not active (user application program running). 1 BDM active and waiting for serial commands. Freescale Semiconductor BKPTEN FTS ...
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... If this tagged opcode ever reaches the end of the instruction queue, . Whenever the host forces the target MCU into active . . The usual recovery strategy is to issue a . (Typically, the host would restore CPU registers and stack values and . ) MC9RS08KA2 Series Data Sheet, Rev Freescale Semiconductor ...
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... BDCBKPT breakpoint register) 1. The RS08 CPU uses only 14 bits of address and occupies the lower 14 bits of the 16-bit AAAA address field. The values of address bits 15 and 14 in AAAA are truncated and thus do not matter. Freescale Semiconductor ...
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... Trace one user instruction at the address in the PC, then return to active back- ground mode Read a block of data from target memory starting from AAAA continuing until a soft-reset is detected Write a block of data to target memory starting at AAAA continuing until a soft-reset is detected Read accumulator (A) Freescale Semiconductor ...
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... HCS08 BDC had separate WRITE_CCR and WRITE_PC commands, the RS08 BDC combined this commands READ_SP (read stack pointer) for HCS08 BDC WRITE_SP (write stack pointer) for HCS08 BDC. Freescale Semiconductor Coding Structure 48/WD/d Write accumulator (A) Read the CCR bits z, c concatenated with ...
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... Chapter 12 Development Support 108 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... Ensure external V current. This will be the greatest risk when the MCU is not consuming power. Examples are system clock is present the clock rate is very low which would reduce overall power consumption. Freescale Semiconductor Table A-1 may affect device reliability or cause Table A-1 ...
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... JA 1s 2s2p 1s 2s2p ) in °C can be obtained from: J × θ and can be neglected. An approximate relationship between P int MC9RS08KA2 Series Data Sheet, Rev will be very SS DD Value Unit ° – 105 °C 225 53 °C/W 115 74 160 98 Eqn. A-1 and T D Freescale Semiconductor J ...
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... Minimum RAM retention supply voltage applied to V Low-voltage Detection threshold Power on RESET (POR) voltage Input high voltage (V > 2.3V) (all digital inputs) DD Input high voltage (1.8 V ≤ V ≤ 2.3 V) (all digital inputs) DD Freescale Semiconductor = K ÷ 273° for K gives: × 273°C) + θ ...
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... V – 0.8 — DD — — — — 40 0.8 — — 0.8 0.8 — — 40 — — 0.2 0.8 — — 7 for pulldown. which is internally clamped to PP and could result DD Freescale Semiconductor Unit μA μA kΩ ...
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... Freescale Semiconductor Figure 12-8. Typical IOH vs. VDD-VOH VDD = 5 V Figure 12-9. Typical IOH vs. VDD-VOH VDD = 3 V Figure 12-10. Typical IOH vs. VDD-VOH VDD = 1.8 V MC9RS08KA2 Series Data Sheet, Rev. 4 Appendix A Electrical Characteristics 113 ...
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... Appendix A Electrical Characteristics Figure 12-13. Typical V 114 Figure 12-11. Typical I vs VDD = 5 V Figure 12-12. Typical I vs VDD = vs MC9RS08KA2 Series Data Sheet, Rev =2mA OH Freescale Semiconductor ...
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... A.6 Supply Current Characteristics Parameter 3 Run supply current measured MHz) Bus 3 Run supply current measured 1.25 MHz) Bus Stop mode supply current Bandgap buffer adder from stop (BGBE = 1) Freescale Semiconductor vs Table A-5. Supply Current Characteristics Symbol V ( DD10 5 3 1.8 RI DD1 5 3 1.8 ...
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... MC9RS08KA2 Series Data Sheet, Rev Typical Max Temp. (° μA 20 μ μA 20 μ μA 20 μ 300 nA 500 300 nA 500 300 nA 500 140 μA 165 μ 140 μA 165 μ 135 μA 160 μ μA 85 μ μA 85 μ μA 80 μA 85 Freescale Semiconductor ...
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... Average internal reference frequency - trimmed DCO output frequency range - untrimmed DCO output frequency range - trimmed Resolution of trimmed DCO output frequency at fixed voltage and temperature Total deviation of trimmed DCO output frequency over voltage and temperature 2,3 FLL acquisition time Freescale Semiconductor vs Symbol AIN ...
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... Figure A-1. Reset Timing MC9RS08KA2 Series Data Sheet, Rev Min Typ Max — 100 — 86 Min Typical Max dc — 10 700 1000 1300 150 — — 1.5 t — — cyc 100 — — — 11 — — 35 — Freescale Semiconductor Unit μs Unit MHz μ ...
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... A.10 FLASH Specifications This section provides details about program/erase times and program-erase endurance for the FLASH memory. For detailed information about program/erase operations, see Freescale Semiconductor t KBIPWS t KBIPW KBI Pin KBI Pin t KBIPW t KBIPWS Figure A-2. KBI Pulse Width Chapter 4, MC9RS08KA2 Series Data Sheet, Rev ...
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... V μs — 40 — — ms — — 2 hours μs — — μs — — μs — — μs — — — — ns — — ns — — ns μs — — — — cycles 100 — years power source is PP Freescale Semiconductor ...
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... WRITE DATA PGM HVEN Next Data applies if programming multiple bytes in a single row, reference 2 V must valid operating voltage before voltage is applied or removed from the V DD Freescale Semiconductor 100 Ω Figure A-3. Example V Filtering PP t prog Next Data Data t pgs t t nvs ...
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... Appendix A Electrical Characteristics MASS HVEN must valid operating voltage before voltage is applied or removed from the V DD 122 nvh1 nvs vps Figure A-5. Flash Mass Erase Timing MC9RS08KA2 Series Data Sheet, Rev rcv t vph pin. PP Freescale Semiconductor ...
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... This following pages contain mechanical specifications for MC9RS08KA2 Series package options: • 6-pin DFN (dual flat no-lead) • 8-pin PDIP (plastic dual in-line pin) • 8-pin NB-SOIC (narrow body small outline integrated circuit) Freescale Semiconductor Table B-1. Device Numbering System Memory RAM Type 6 DFN 63 bytes ...
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... Appendix B Ordering Information and Mechanical Drawings 124 MC9RS08KA2 Series Data Sheet, Rev. 4 Freescale Semiconductor ...
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... Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer ...