C8051T632-GM Silicon Laboratories Inc, C8051T632-GM Datasheet - Page 119
C8051T632-GM
Manufacturer Part Number
C8051T632-GM
Description
IC MCU 4KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Specifications of C8051T632-GM
Program Memory Type
OTP
Program Memory Size
4KB (4K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1460-5
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A Port mismatch event may be used to generate an interrupt or wake the device from a low power mode,
such as IDLE or SUSPEND. See the Interrupts and Power Options chapters for more details on interrupt
and wake-up sources.
SFR Definition 20.3. P0MASK: Port 0 Mask Register
SFR Address = 0xFE
SFR Definition 20.4. P0MAT: Port 0 Match Register
SFR Address = 0xFD
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
P0MASK[7:0]
P0MAT[7:0]
Name
Name
7
0
7
1
Port 0 Mask Value.
Selects P0 pins to be compared to the corresponding bits in P0MAT.
0: P0.n pin logic value is ignored and cannot cause a Port Mismatch event.
1: P0.n pin logic value is compared to P0MAT.n.
Port 0 Match Value.
Match comparison value used on Port 0 for bits in P0MASK which are set to 1.
0: P0.n pin logic value is compared with logic LOW.
1: P0.n pin logic value is compared with logic HIGH.
6
0
6
1
5
0
5
1
Rev. 1.0
P0MASK[7:0]
4
0
4
1
P0MAT[7:0]
R/W
R/W
Function
Function
3
0
3
1
C8051T630/1/2/3/4/5
2
0
2
1
1
0
1
1
0
0
0
1
119
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