C8051T632-GM Silicon Laboratories Inc, C8051T632-GM Datasheet - Page 8
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C8051T632-GM
Manufacturer Part Number
C8051T632-GM
Description
IC MCU 4KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Specifications of C8051T632-GM
Program Memory Type
OTP
Program Memory Size
4KB (4K x 8)
Package / Case
20-QFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
17
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 16x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
On-chip Adc
16-ch x 10-bit
On-chip Dac
16-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1460-5
C8051T630/1/2/3/4/5
21. SMBus
22. UART0
23. Enhanced Serial Peripheral Interface (SPI0)
24. Timers
25. Programmable Counter Array
8
Figure 20.4. Crossbar Priority Decoder with Crystal Pins Skipped ....................... 115
Figure 21.1. SMBus Block Diagram ...................................................................... 127
Figure 21.2. Typical SMBus Configuration ............................................................ 128
Figure 21.3. SMBus Transaction ........................................................................... 129
Figure 21.4. Typical SMBus SCL Generation ........................................................ 131
Figure 21.5. Typical Master Write Sequence ........................................................ 140
Figure 21.6. Typical Master Read Sequence ........................................................ 141
Figure 21.7. Typical Slave Write Sequence .......................................................... 142
Figure 21.8. Typical Slave Read Sequence .......................................................... 143
Figure 22.1. UART0 Block Diagram ...................................................................... 148
Figure 22.2. UART0 Baud Rate Logic ................................................................... 149
Figure 22.3. UART Interconnect Diagram ............................................................. 150
Figure 22.4. 8-Bit UART Timing Diagram .............................................................. 150
Figure 22.5. 9-Bit UART Timing Diagram .............................................................. 151
Figure 22.6. UART Multi-Processor Mode Interconnect Diagram ......................... 152
Figure 23.1. SPI Block Diagram ............................................................................ 156
Figure 23.2. Multiple-Master Mode Connection Diagram ...................................... 158
Figure 23.3. 3-Wire Single Master and 3-Wire
Figure 23.4. 4-Wire Single Master Mode
Figure 23.5. Master Mode Data/Clock Timing ....................................................... 161
Figure 23.6. Slave Mode Data/Clock Timing (CKPHA = 0) ................................... 161
Figure 23.7. Slave Mode Data/Clock Timing (CKPHA = 1) ................................... 162
Figure 23.8. SPI Master Timing (CKPHA = 0) ....................................................... 166
Figure 23.9. SPI Master Timing (CKPHA = 1) ....................................................... 166
Figure 23.10. SPI Slave Timing (CKPHA = 0) ....................................................... 167
Figure 23.11. SPI Slave Timing (CKPHA = 1) ....................................................... 167
Figure 24.1. T0 Mode 0 Block Diagram ................................................................. 172
Figure 24.2. T0 Mode 2 Block Diagram ................................................................. 173
Figure 24.3. T0 Mode 3 Block Diagram ................................................................. 174
Figure 24.4. Timer 2 16-Bit Mode Block Diagram ................................................. 179
Figure 24.5. Timer 2 8-Bit Mode Block Diagram ................................................... 180
Figure 24.6. Timer 2 Low-Frequency Oscillation Capture Mode Block Diagram ... 181
Figure 24.7. Timer 3 16-Bit Mode Block Diagram ................................................. 185
Figure 24.8. Timer 3 8-Bit Mode Block Diagram ................................................... 186
Figure 24.9. Timer 3 Low-Frequency Oscillation Capture Mode Block Diagram ... 187
Figure 25.1. PCA Block Diagram ........................................................................... 191
Figure 25.2. PCA Counter/Timer Block Diagram ................................................... 192
Figure 25.3. PCA Interrupt Block Diagram ............................................................ 193
Single Slave Mode Connection Diagram .......................................... 159
and 4-Wire Slave Mode Connection Diagram ................................... 159
Rev. 1.0