C8051T631-GM Silicon Laboratories Inc, C8051T631-GM Datasheet - Page 5
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C8051T631-GM
Manufacturer Part Number
C8051T631-GM
Description
IC MCU 8KB 20PIN QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051T63xr
Specifications of C8051T631-GM
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
17
Program Memory Size
8KB (8K x 8)
Program Memory Type
OTP
Ram Size
768 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-QFN
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
768 B
Interface Type
UART, SPI, SMBus
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
17
Number Of Timers
4 x 16-bit
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051T630DK
Minimum Operating Temperature
- 40 C
For Use With
336-1464 - KIT DEV FOR C8051T630 FAMILY
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Details
Other names
336-1459-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051T631-GM
Manufacturer:
Silicon
Quantity:
91
21. SMBus................................................................................................................... 127
22. UART0 ................................................................................................................... 148
23. Enhanced Serial Peripheral Interface (SPI0) ..................................................... 156
24. Timers ................................................................................................................... 169
20.3. Priority Crossbar Decoder ............................................................................. 114
20.4. Port I/O Initialization ...................................................................................... 116
20.5. Port Match ..................................................................................................... 118
20.6. Special Function Registers for Accessing and Configuring Port I/O ............. 121
21.1. Supporting Documents .................................................................................. 128
21.2. SMBus Configuration..................................................................................... 128
21.3. SMBus Operation .......................................................................................... 128
21.4. Using the SMBus........................................................................................... 130
21.5. SMBus Transfer Modes................................................................................. 140
21.6. SMBus Status Decoding................................................................................ 143
22.1. Enhanced Baud Rate Generation.................................................................. 149
22.2. Operational Modes ........................................................................................ 150
22.3. Multiprocessor Communications ................................................................... 152
23.1. Signal Descriptions........................................................................................ 157
23.2. SPI0 Master Mode Operation ........................................................................ 158
23.3. SPI0 Slave Mode Operation .......................................................................... 159
23.4. SPI0 Interrupt Sources .................................................................................. 160
23.5. Serial Clock Phase and Polarity .................................................................... 160
23.6. SPI Special Function Registers ..................................................................... 162
24.1. Timer 0 and Timer 1 ...................................................................................... 171
21.3.1. Transmitter Vs. Receiver....................................................................... 129
21.3.2. Arbitration.............................................................................................. 129
21.3.3. Clock Low Extension............................................................................. 129
21.3.4. SCL Low Timeout.................................................................................. 129
21.3.5. SCL High (SMBus Free) Timeout ......................................................... 130
21.4.1. SMBus Configuration Register.............................................................. 130
21.4.2. SMB0CN Control Register .................................................................... 134
21.4.3. Hardware Slave Address Recognition .................................................. 136
21.4.4. Data Register ........................................................................................ 139
21.5.1. Write Sequence (Master) ...................................................................... 140
21.5.2. Read Sequence (Master) ...................................................................... 141
21.5.3. Write Sequence (Slave) ........................................................................ 142
21.5.4. Read Sequence (Slave) ........................................................................ 143
22.2.1. 8-Bit UART ............................................................................................ 150
22.2.2. 9-Bit UART ............................................................................................ 151
23.1.1. Master Out, Slave In (MOSI)................................................................. 157
23.1.2. Master In, Slave Out (MISO)................................................................. 157
23.1.3. Serial Clock (SCK) ................................................................................ 157
23.1.4. Slave Select (NSS) ............................................................................... 157
21.4.2.1. Software ACK Generation ............................................................ 134
21.4.2.2. Hardware ACK Generation ........................................................... 134
Rev. 1.0
C8051T630/1/2/3/4/5
5