C8051F553-IM Silicon Laboratories Inc, C8051F553-IM Datasheet - Page 251
![IC 8051 MCU 32K FLASH 24-QFN](/photos/12/15/121587/c8051f9xx_24-qfn_sml.jpg)
C8051F553-IM
Manufacturer Part Number
C8051F553-IM
Description
IC 8051 MCU 32K FLASH 24-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F55xr
Specifications of C8051F553-IM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
24-QFN
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
18
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 18x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
18
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F540DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1686-5
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SFR Definition 24.3. SPI0CKR: SPI0 Clock Rate
SFR Address = 0xA2; SFR Page = 0x00
SFR Definition 24.4. SPI0DAT: SPI0 Data
SFR Address = 0xA3; SFR Page = 0x00
Name
Reset
Name
Reset
Bit
7:0
Bit
7:0
Type
Type
Bit
Bit
SPI0DAT[7:0] SPI0 Transmit and Receive Data.
SCR[7:0]
Name
Name
7
0
7
0
SPI0 Clock Rate.
These bits determine the frequency of the SCK output when the SPI0 module is
configured for master mode operation. The SCK clock frequency is a divided ver-
sion of the system clock, and is given in the following equation, where SYSCLK is
the system clock frequency and SPI0CKR is the 8-bit value held in the SPI0CKR
register.
for 0 <= SPI0CKR <= 255
Example: If SYSCLK = 2 MHz and SPI0CKR = 0x04,
The SPI0DAT register is used to transmit and receive SPI0 data. Writing data to
SPI0DAT places the data into the transmit buffer and initiates a transfer when in
Master Mode. A read of SPI0DAT returns the contents of the receive buffer.
f SCK
f SCK
6
0
6
0
=
=
----------------------------- -
2
--------------------------------------------------------------- -
2
2000000
x
x
5
0
5
0
4
SPI0CKR[7:0]
+
SYSCLK
1
Rev. 1.1
SPI0DAT[7:0]
4
0
4
0
SCR[7:0]
f SCK
+
R/W
R/W
1
Function
Function
=
3
0
3
0
200 kHz
C8051F55x/56x/57x
2
0
2
0
1
0
1
0
0
0
0
0
251
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