C8051F563-IM Silicon Laboratories Inc, C8051F563-IM Datasheet - Page 132
![IC 8051 MCU 32K FLASH 32-QFN](/photos/12/26/122657/c8051f563-im_sml.jpg)
C8051F563-IM
Manufacturer Part Number
C8051F563-IM
Description
IC 8051 MCU 32K FLASH 32-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F56xr
Specifications of C8051F563-IM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
32-QFN
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
25
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 25x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
2304 B
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
25
Operating Supply Voltage
1.8 V to 5.25 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F560DK
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1691 - KIT DEVELOPMENT FOR C8051F560
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1699-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F563-IM
Manufacturer:
Silicon Labs
Quantity:
135
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C8051F55x/56x/57x
SFR Definition 14.4. CCH0CN: Cache Control
SFR Address = 0xE3; SFR Page = 0x0F
SFR Definition 14.5. ONESHOT: Flash Oneshot Period
SFR Address = 0xBE; SFR Page = 0x0F
132
Name Reserved
Reset
Name
Reset
7:6
4:1
7:4
3:0
Bit
Bit
Type
Type
5
0
Bit
Bit
PERIOD[3:0] Oneshot Period Control Bits.
Reserved
Reserved
CHBLKW
CHPFEN
Name
Unused
Name
R/W
R
7
0
7
0
Must Write 00b
Cache Prefect Enable Bit.
0: Prefetch engine is disabled.
1: Prefetch engine is enabled.
Must Write 0000b.
Block Write Enable Bit.
This bit allows block writes to Flash memory from firmware.
0: Each byte of a software Flash write is written individually.
1: Flash bytes are written in groups of two.
Reserved
Read = 0000b. Write = don’t care.
These bits limit the internal Flash read strobe width as follows. When the Flash read
strobe is de-asserted, the Flash memory enters a low-power state for the remainder
of the system clock cycle.
R/W
R
6
0
6
0
CHPFEN
R/W
R
5
1
5
0
FLASH
Reserved
R/W
Rev. 1.1
R
4
0
4
0
RDMAX
Function
Reserved
Function
=
R/W
R/W
5ns
3
0
3
1
+
PERIOD 5ns
Reserved
R/W
R/W
2
0
2
1
PERIOD[3:0]
Reserved
R/W
R/W
1
0
1
1
CHBLKW
R/W
R/W
0
0
0
1
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