C8051F505-IM Silicon Laboratories Inc, C8051F505-IM Datasheet - Page 295
![IC 8051 MCU 32K FLASH 48-QFN](/photos/12/27/122700/c8051f505-im_sml.jpg)
C8051F505-IM
Manufacturer Part Number
C8051F505-IM
Description
IC 8051 MCU 32K FLASH 48-QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F50xr
Specifications of C8051F505-IM
Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
48-QFN
Mfg Application Notes
LIN Bootloader AppNote
Core Processor
8051
Core Size
8-Bit
Speed
50MHz
Connectivity
EBI/EMI, SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
40
Ram Size
4.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.25 V
Data Converters
A/D 32x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Processor Series
C8051F5x
Core
8051
Data Bus Width
8 bit
Data Ram Size
4.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
50 MHz
Number Of Programmable I/os
40
Number Of Timers
4
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F500DK
Minimum Operating Temperature
- 40 C
On-chip Adc
32-ch x 12-bit
A/d Bit Size
12 bit
A/d Channels Available
32
Height
0.88 mm
Length
7 mm
Supply Voltage (max)
5.25 V
Supply Voltage (min)
1.8 V
Width
7 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
336-1527 - KIT DEV FOR C8051F50X
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1521-5
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F505-IM
Manufacturer:
Silicon Labs
Quantity:
135
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27.3.5.2. 9/10/11-bit Pulse Width Modulator Mode
The duty cycle of the PWM output signal in 9/10/11-bit PWM mode should be varied by writing to an “Auto-
Reload” Register, which is dual-mapped into the PCA0CPHn and PCA0CPLn register locations. The data
written to define the duty cycle should be right-justified in the registers. The auto-reload registers are
accessed (read or written) when the bit ARSEL in PCA0PWM is set to 1. The capture/compare registers
are accessed when ARSEL is set to 0.
When the least-significant N bits of the PCA0 counter match the value in the associated module’s cap-
ture/compare register (PCA0CPn), the output on CEXn is asserted high. When the counter overflows from
the Nth bit, CEXn is asserted low (see Figure 27.9). Upon an overflow from the Nth bit, the COVF flag is
set, and the value stored in the module’s auto-reload register is loaded into the capture/compare register.
The value of N is determined by the CLSEL bits in register PCA0PWM.
The 9, 10 or 11-bit PWM mode is selected by setting the ECOMn and PWMn bits in the PCA0CPMn regis-
ter, and setting the CLSEL bits in register PCA0PWM to the desired cycle length (other than 8-bits). If the
MATn bit is set to 1, the CCFn flag for the module will be set each time a comparator match (rising edge)
occurs. The COVF flag in PCA0PWM can be used to detect the overflow (falling edge), which will occur
every 512 (9-bit), 1024 (10-bit) or 2048 (11-bit) PCA clock cycles. The duty cycle for 9/10/11-Bit PWM
Mode is given in Equation 27.2, where N is the number of bits in the PWM cycle.
Important Note About PCA0CPHn and PCA0CPLn Registers : When writing a 16-bit value to the
PCA0CPn registers, the low byte should always be written first. Writing to PCA0CPLn clears the ECOMn
bit to 0; writing to PCA0CPHn sets ECOMn to 1.
A 0% duty cycle may be generated by clearing the ECOMn bit to 0.
PCA0CPLn
Write to
Reset
PCA0CPHn
A
R
S
E
L
0
Write to
C
O
PCA0PWM
E
V
C
O
V
F
x
0
ENB
ENB
1
C
L
S
E
L
1
0
C
L
S
E
L
0
0
W
M
P
1
6
n
0
Equation 27.3. 9, 10, and 11-Bit PWM Duty Cycle
E
C
O
M
n
PCA0CPMn
C
A
P
P
n
0 0 x 0
Figure 27.8. PCA 8-Bit PWM Mode Diagram
C
N
A
P
n
M
A
T
n
O
G
T
n
W
M
P
n
E
C
C
F
n
x
PCA Timebase
Duty Cycle
Enable
=
PCA0CPHn
Comparator
PCA0CPLn
Rev. 1.2
PCA0L
----------------------------------------------- -
8-bit
2 N PCA0CPn
–
2 N
Overflow
COVF
match
S
R
C8051F50x/F51x
SET
CLR
Q
Q
CEXn
Crossbar
Port I/O
295
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