C8051F504-IM Silicon Laboratories Inc, C8051F504-IM Datasheet - Page 212

• Manufacturer Part Number: C8051F504-IM
• Description: IC 8051 MCU 32K FLASH 48-QFN
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F50xr

Specifications of C8051F504-IM

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 48-QFN
• Mfg Application Notes: LIN Bootloader AppNote
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 50MHz
• Connectivity: EBI/EMI, SMBus (2-Wire/I²C), CAN, LIN, SPI, UART/USART
• Peripherals: POR, PWM, Temp Sensor, WDT
• Number Of I /o: 40
• Ram Size: 4.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.25 V
• Data Converters: A/D 32x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: C8051F5x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 4.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 50 MHz
• Number Of Programmable I/os: 40
• Number Of Timers: 4
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F500DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 32-ch x 12-bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1527 - KIT DEV FOR C8051F50X
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1519-5

C8051F50x/F51x
LIN Register Definition 21.5. LIN0CTRL: LIN0 Control Register
Indirect Address = 0x08
212
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
WUPREQ
RSTERR
RSTINT
STREQ
SLEEP
DTACK
Name
STOP
TXRX
STOP
W
7
0
Stop Communication Processing Bit. (slave mode only)
This bit always reads as 0.
0: No effect.
1: Block the processing of LIN communications until the next SYNC BREAK signal.
Sleep Mode Bit. (slave mode only)
0: Wake the device after receiving a Wakeup interrupt.
1: Put the device into sleep mode after receiving a Sleep Mode frame or a bus idle
timeout.
Transmit / Receive Selection Bit.
0: Current frame is a receive operation.
1: Current frame is a transmit operation.
Data Acknowledge Bit. (slave mode only)
Set to 1 after handling a data request interrupt to acknowledge the transfer. The bit
will automatically be cleared to 0 by the LIN controller.
Reset Interrupt Bit.
This bit always reads as 0.
0: No effect.
1: Reset the LININT bit (LIN0ST.3).
Reset Error Bit.
This bit always reads as 0.
0: No effect.
1: Reset the error bits in LIN0ST and LIN0ERR.
Wakeup Request Bit.
Set to 1 to terminate sleep mode by sending a wakeup signal. The bit will automati-
cally be cleared to 0 by the LIN controller.
Start Request Bit. (master mode only)
1: Start a LIN transmission. This should be set only after loading the identifier, data
length and data buffer if necessary.
The bit is reset to 0 upon transmission completion or error detection.
SLEEP
R/W
6
0
TXRX
R/W
5
0
DTACK
R/W
Rev. 1.2
4
0
Function
RSTINT
W
3
0
RSTERR
W
2
0
WUPREQ
R/W
1
0
STREQ
R/W
0
0