R5F21262SNFP#U0 Renesas Electronics America, R5F21262SNFP#U0 Datasheet - Page 289
![IC R8C/26 MCU FLASH 32LQFP](/photos/12/27/122729/r5f21262snfp_u0_sml.jpg)
R5F21262SNFP#U0
Manufacturer Part Number
R5F21262SNFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21262SNFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
16.2.1
16.2.1.1
The transfer clock can be selected from among seven internal clocks (f1/256, f1/128, f1/64, f1/32, f1/16, f1/8,
and f1/4) and an external clock.
When using clock synchronous serial I/O with chip select, set the SCKS bit in the SSMR2 register to 1 and
select the SSCK pin as the serial clock pin.
When the MSS bit in the SSCRH register is set to 1 (operates as master device), an internal clock can be
selected and the SSCK pin functions as output. When transfer is started, the SSCK pin outputs clocks of the
transfer rate selected by bits CKS0 to CKS2 in the SSCRH register.
When the MSS bit in the SSCRH register is set to 0 (operates as slave device), an external clock can be selected
and the SSCK pin functions as input.
The association between the transfer clock polarity, phase and data changes according to the combination of the
SSUMS bit in the SSMR2 register and bits CPHS and CPOS in the SSMR register.
Figure 16.10 shows the Association between Transfer Clock Polarity, Phase, and Transfer Data.
Also, the MSB-first transfer or LSB-first transfer can be selected by setting the MLS bit in the SSMR register.
When the MLS bit is set to 1, transfer is started from the LSB and proceeds to the MSB. When the MLS bit is
set to 0, transfer is started from the MSB and proceeds to the LSB.
Sep 26, 2008
Transfer Clock
Association between Transfer Clock Polarity, Phase, and Data
Page 270 of 453
16. Clock Synchronous Serial Interface
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