R5F21262SDFP#U0 Renesas Electronics America, R5F21262SDFP#U0 Datasheet - Page 135
![IC R8C/26 MCU FLASH 32LQFP](/photos/12/27/122743/r5f21262sdfp_u0_sml.jpg)
R5F21262SDFP#U0
Manufacturer Part Number
R5F21262SDFP#U0
Description
IC R8C/26 MCU FLASH 32LQFP
Manufacturer
Renesas Electronics America
Series
R8C/2x/26r
Datasheet
1.R5F21272SDFPU0.pdf
(487 pages)
Specifications of R5F21262SDFP#U0
Core Processor
R8C
Core Size
16/32-Bit
Speed
20MHz
Connectivity
I²C, LIN, SIO, SSU, UART/USART
Peripherals
LED, POR, Voltage Detect, WDT
Number Of I /o
25
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.2 V ~ 5.5 V
Data Converters
A/D 12x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-LQFP
For Use With
R0K521276S000BE - KIT DEV RSK-R8C/26-29R0E521000EPB00 - PROBE EMULATOR FOR PC7501
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
R5F21262SDFP#U0R5F21262SDFP#W4
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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R8C/26 Group, R8C/27 Group
Rev.2.10
REJ09B0278-0210
Figure 12.4
Interrupt Control Register
b7 b6 b5 b4
NOTES:
1.
2.
Rew rite the interrupt control register w hen the interrupt request w hich is applicable for the register is not generated.
Refer to 12.6.5 Changing Interrupt Control Register Contents.
The IICSEL bit in the PMR register sw itches functions.
Sep 26, 2008
b3 b2 b1 b0
Registers TRCIC and SSUIC/IICIC
Bit Symbol
(b7-b4)
Page 116 of 453
ILVL0
ILVL1
ILVL2
(1)
SSUIC/IICIC
TRCIC
—
IR
Symbol
(2)
Interrupt priority level select bits
Interrupt request bit
Nothing is assigned. If necessary, set to 0.
When read, the content is undefined.
Bit Name
Address
0047h
004Fh
b2 b1 b0
0 0 0 : Level 0 (interrupt disable)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Requests no interrupt
1 : Requests interrupt
XXXXX000b
XXXXX000b
After Reset
Function
12. Interrupts
RW
RW
RW
RW
RO
—
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