M30620FCPGP#U5C Renesas Electronics America, M30620FCPGP#U5C Datasheet - Page 128
M30620FCPGP#U5C
Manufacturer Part Number
M30620FCPGP#U5C
Description
IC M16C MCU FLASH 128K 100LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30620FCPGP#U5C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
85
Program Memory Size
128KB (128K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
100-LQFP
Package
100LQFP
Family Name
M16C
Maximum Speed
24 MHz
Operating Supply Voltage
3.3|5 V
Data Bus Width
16|32 Bit
Number Of Programmable I/os
87
Interface Type
UART
On-chip Adc
26-chx10-bit
On-chip Dac
2-chx8-bit
Number Of Timers
11
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
12.5
Figure 12.3
Interrupt Control Register
The following describes how to enable/disable the maskable interrupts, and how to set the priority in which order
they are accepted. What is explained here does not apply to nonmaskable interrupts.
Use the I flag in the FLG register, IPL, and ILVL2 to ILVL0 bits in the each interrupt control register to enable/
disable the maskable interrupts. Whether an interrupt is requested is indicated by the IR bit in the each interrupt
control register.
Figure 12.3 and Figure 12.4 show the Interrupt Control Registers.
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1.
2.
3. Use the IFSR2A register to select.
This bit can only be reset by w riting “0” (Do not w rite “1”).
To rew rite the interrupt control registers, do so at a point that does not generate the interrupt request for that register.
For details, refer to 24.6 Interrupt.
Interrupt Control
Jan 10, 2006
Interrupt Control Registers (1)
TB5IC
TB4IC/U1BCNIC
TB3IC/U0BCNIC
BCNIC
DM0IC, DM1IC
KUPIC
ADIC
S0TIC to S2TIC
S0RIC to S2RIC
TA0IC to TA4IC
TB0IC to TB2IC
Bit Symbol
(b7-b4)
Symbol
ILVL0
ILVL1
ILVL2
—
IR
Page 111 of 390
(2)
Interrupt Priority Level Select Bit
Interrupt Request Bit
Nothing is assigned. When w rite, set to “0”.
When read, their contents are indeterminate.
(3)
(3)
Bit Name
0045h
0046h
0047h
004Ah
004Bh, 004Ch
004Dh
004Eh
0051h, 0053h, 004Fh
0052h, 0054h, 0050h
0055h to 0059h
005Ah to 005Ch
Address
b2 b1 b0
0 0 0 : Level 0 (interrupt disabled)
0 0 1 : Level 1
0 1 0 : Level 2
0 1 1 : Level 3
1 0 0 : Level 4
1 0 1 : Level 5
1 1 0 : Level 6
1 1 1 : Level 7
0 : Interrupt not requested
1 : Interrupt requested
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
XXXXX000b
After Reset
Function
12. Interrupt
RW
RW
RW
RW
RW
—
(1)
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