M30625FGPGP#U9C Renesas Electronics America, M30625FGPGP#U9C Datasheet - Page 184
![IC M16C MCU FLASH 128LQFP](/photos/12/29/122943/m30625fgpgp_u9c_sml.jpg)
M30625FGPGP#U9C
Manufacturer Part Number
M30625FGPGP#U9C
Description
IC M16C MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Datasheets
1.QSK-62P_PLUS.pdf
(103 pages)
2.M30622SAFPU5.pdf
(308 pages)
3.M30620SPGPU3C.pdf
(423 pages)
Specifications of M30625FGPGP#U9C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
20K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Manufacturer
Quantity
Price
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 16.2
Three-Phase Control Register 0
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1.
2.
3.
4.
5.
6.
7.
8.
Mode
Timing to Transf er f rom the IDB0
and IDB1 Registers to Three Phase
Output Shif t Register
Timing to Trigger the Dead Time
Timer when the INV16 Bit=0
INV13 Bit
9.
Set the INVC0 register af ter the PRC1 bit in the PRCR register is set to “1” (write enable).
Rewrite the INV00 to INV02 and INV06 bits when Timers A1, A2, A4 and B2 stop.
Set the INV01 bit to “1” af ter setting the ICTB2 register.
The INV00 and INV01 bits are enabled only when the INV11 bit is set to “1” (three-phase mode 1). The ICTB2 counter is incremented by
one ev ery time Timer B2 underf lows, regardless of INV00 and INV01 bit settings, when the INV11 bit is set to “0” (three-phase mode).
When setting the INV01 bit to “1”, set Timer A1 count start f lag bef ore the f irst Timer B2 underf low.
When the INV00 bit is set to “1”, the f irst interrupt is generated when Timer B2 underf lows n -1 times, if n is the v alue set in the ICTB2
counter. Subsequent interrupts are generated ev ery n times Timer B2 underf lows.
Set the INV02 bit to “1” to operate the dead time timer, U-, V-and W-phase output control circuits and ICTB2 counter.
The U, U
when the f ollowing conditions are all met.
The INV03 bit is set to “0” when the f ollowings conditions are all met.
When both the INVC04 and INVC05 bits are set to “1”, the INVC03 bit is set to “0”.
The INV05 bit can not be set to “1” by program. Set the INV04 bit to “0”, as well, when setting the INV05 bit to “0”.
The f ollowing table describes how the INV06 bit works.
Transf er trigger : Timer B2 underf lows and write to the INV07 bit, or write to the TB2 register when INV10 = 1
When the INV06 bit is set to “1”, set the INV11 bit to “0” (three-phase mode 0) and the PWCON bit in the TB2SC register to “0” (reload
Timer B2 with Timer B2 underf low).
When the INVC03 bit is set to “1”, the pins applied to U/V/W output three-phase PWM.
Jan 10, 2006
• The INV02 bit is set to “1” (three-phase control timer f unction)
• The INV03 bit is set to “0” (three-phase control timer output disabled)
• Direction registers of each port are set to “0” (input mode)
• Reset
• A concurrent activ e state occurs while INV04 bit is set to “1”
• The INV03 bit is set to “0” by program
• A signal applied to the NMI
__
, V, V
INVC0 Register
Item
__
, W and W
Bit Symbol
Symbol
INVC0
INV00
INV01
INV02
INV03
INV04
INV05
INV06
INV07
___
Page 167 of 390
_____
pins, including pins shared with other output f unctions, are all placed in high-impedance states
pin changes “H” to “L”
Interrupt Enable Output
Polarity Select Bit
Interrupt Enable Output
Specification Bit
Mode Select Bit
Output Control Bit
Positiv e and Negativ e-Phases
Concurrent Activ e Disable
Function Enable Bit
Positiv e and Negativ e-Phases
Concurrent Activ e Output Detect
Flag
Modulation Mode
Select
Softw are Trigger Select
Triangular wav e modulation mode
Transf erred once by generating a transf er trigger
af ter setting the IDB0 and IDB1 registers
On the f alling edge of a one-shot pulse of the timer
A1, A2 or A4
Enabled when the INV11 bit=1 and the INV06 bit=0
(1)
(7)
(8, 9)
Address
Bit Name
0348h
(4, 5)
(2, 3)
(3)
(5, 6)
INV06=0
0 : The ICTB2 counter is incremented by one on the
1 : The ICTB2 counter is incremented by one on the
0 : ICTB2 counter is incremented by one when Timer B2
1 : Selected by the INV00 bit
0 : No three-phase control timer functions
1 : Three-phase control timer function
0 : Disables three-phase control timer output
1 : Enables three-phase control timer output
0 : Enables concurrent active output
1 : Disables concurrent active output
0 : Not detected
1 : Detected
0 : Triangular w ave modulation mode
1 : Saw tooth w ave modulation mode
Transf er trigger is generated when the INV07 bit is set to “1”.
Trigger to the dead time timer is also generated when setting
the INV06 bit to “1”. Its v alue is “0” when read.
rising edge of Timer A1 reload control signal
f alling edge of Timer A1 reload control signal
underf lows
16. Three-Phase Motor Control Timer Function
Sawtooth wav e modulation mode
Transf erred ev ery time a transf er trigger
is generated
By a transf er trigger, or the f alling edge of
a one-shot pulse of the timer A1, A2 or A4
Disabled
Function
After Reset
INV06=1
00h
RW
RW
RW
RW
RW
RW
RW
RW
RW
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