M30627FJPGP#U9C Renesas Electronics America, M30627FJPGP#U9C Datasheet - Page 147
M30627FJPGP#U9C
Manufacturer Part Number
M30627FJPGP#U9C
Description
IC M16C/62P MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30627FJPGP#U9C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-20°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30627FJPGP#U9CM30627FJPGP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
Figure 14.4
DMAi Control Register (i=0,1)
b7 b6 b5 b4 b3 b2 b1 b0
NOTES :
1.
2.
The DMAS bit can be set to “0” by w riting “0” in a program (This bit remains unchanged even if “1” is w ritten).
At least one of the DAD and DSD bits must be “0” (address direction fixed).
Jan 10, 2006
DM0CON and DM1CON Register
Bit Symbol
DM0CON
DM1CON
DMASL
(b7-b6)
Symbol
DMBIT
DMAS
DMAE
DSD
DAD
Page 130 of 390
—
Transfer Unit Bit Select Bit
Repeat Transfer Mode Select Bit
DMA Request Bit
DMA Enable Bit
Source Address Direction Select
Bit
Destination Address Direction Select
Bit
Nothing is assigned. When w rite, set to “0”.
When read, their contents are “0”.
(2)
(2)
Address
Bit Name
002Ch
003Ch
0 : 16 bits
1 : 8 bits
0 : Single transfer
1 : Repeat transfer
0 : DMA not requested
1 : DMA requested
0 : Disabled
1 : Enabled
0 : Fixed
1 : Forw ard
0 : Fixed
1 : Forw ard
After Reset
00000X00b
00000X00b
Function
14. DMAC
RW
RW
RW
RW
RW
RW
RW
—
(1)
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