M30627FJPGP#U7C Renesas Electronics America, M30627FJPGP#U7C Datasheet - Page 230
![IC M16C/62P MCU FLASH 128LQFP](/photos/12/30/123038/m30627fjpgp_u7c_sml.jpg)
M30627FJPGP#U7C
Manufacturer Part Number
M30627FJPGP#U7C
Description
IC M16C/62P MCU FLASH 128LQFP
Manufacturer
Renesas Electronics America
Series
M16C™ M16C/60r
Specifications of M30627FJPGP#U7C
Core Processor
M16C/60
Core Size
16-Bit
Speed
24MHz
Connectivity
I²C, IEBus, UART/USART
Peripherals
DMA, WDT
Number Of I /o
111
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
31K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 26x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
128-LQFP
For Use With
867-1000 - KIT QUICK START RENESAS 62PR0K33062PS001BE - R0K33062P STARTER KITR0K33062PS000BE - KIT EVAL STARTER FOR M16C/62PM3062PT3-CPE-3 - EMULATOR COMPACT M16C/62P/30P
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
M30627FJPGP#U7CM30627FJPGP#U3C
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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M16C/62P Group (M16C/62P, M16C/62PT)
Rev.2.41
REJ09B0185-0241
17.1.3.4
17.1.3.5
17.1.3.6
17.1.3.7
Data is transmitted/received using a transfer clock like the one shown in Figure 17.26 Transfer to UiRB
Register and Interrupt Timing.
The CSC bit in the UiSMR2 register is used to synchronize the internally generated clock (internal SCLi) and
an external clock supplied to the SCLi pin. In cases when the CSC bit is set to “1” (clock synchronization
enabled), if a falling edge on the SCLi pin is detected while the internal SCLi is high, the internal SCLi goes
low, at which time the value of the UiBRG register is reloaded with and starts counting in the low-level interval.
If the internal SCLi changes state from low to high while the SCLi pin is low, counting stops, and when the
SCLi pin goes high, counting restarts.
In this way, the UARTi transfer clock is comprised of the logical product of the internal SCLi and SCLi pin
signal. The transfer clock works from a half period before the falling edge of the internal SCLi 1st bit to the
rising edge of the 9th bit. To use this function, select an internal clock for the transfer clock.
The SWC bit in the UiSMR2 register allows to select whether the SCLi pin should be fixed to or freed from
low-level output at the falling edge of the 9th clock pulse.
If the SCLHI bit in the UiSMR4 register is set to “1” (enabled), SCLi output is turned off (placed in the high-
impedance state) when a stop condition is detected.
Setting the SWC2 bit in the UiSMR2 register = 1 (0 output) makes it possible to forcibly output a low-level
signal from the SCLi pin even while sending or receiving data. Clearing the SWC2 bit to “0” (transfer clock)
allows the transfer clock to be output from or supplied to the SCLi pin, instead of outputting a low-level signal.
If the SWC9 bit in the UiSMR4 register is set to “1” (SCL hold low enabled) when the CKPH bit in the
UiSMR3 register = 1, the SCLi pin is fixed to low-level output at the falling edge of the clock pulse next to the
9th. Setting the SWC9 bit = 0 (SCL hold low disabled) frees the SCLi pin from low-level output.
The data written to the UiTB register bit 7 to bit 0 (D7 to D0) is sequentially output beginning with D7.
The 9th bit (D8) is ACK or NACK.
The initial value of SDAi transmit output can only be set when IICM = 1 (I
bits in the UiMR register = 000b (Serial interface disabled).
The DL2 to DL0 bits in the UiSMR3 register allow to add no delays or a delay of 2 to 8 UiBRG count source
clock cycles to SDAi output.
Setting the SDHI bit in the UiSMR2 register = 1 (SDA output disabled) forcibly places the SDAi pin in the
high-impedance state. Do not write to the SDHI bit synchronously with the rising edge of the UARTi transfer
clock. This is because the ABT bit may inadvertently be set to “1” (detected).
When the IICM2 bit = 0, the 1st to 8th bits (D7 to D0) of received data are stored in the UiRB register bit 7 to
bit 0. The 9th bit (D8) is ACK or NACK.
When the IICM2 bit = 1, the 1st to 7th bits (D7 to D1) of received data are stored in the UiRB register bit 6 to
bit 0 and the 8th bit (D0) is stored in the UiRB register bit 8. Even when the IICM2 bit = 1, providing the CKPH
bit = 1, the same data as when the IICM2 bit = 0 can be read out by reading the UiRB register after the rising
edge of the corresponding clock pulse of 9th bit.
If the STSPSEL bit in the UiSMR4 register is set to “0” (start and stop conditions not generated) and the ACKC
bit in the UiSMR4 register is set to “1” (ACK data output), the value of the ACKD bit in the UiSMR4 register is
output from the SDAi pin.
If the IICM2 bit = 0, a NACK interrupt request is generated if the SDAi pin remains high at the rising edge of
the 9th bit of transmit clock pulse. An ACK interrupt request is generated if the SDAi pin is low at the rising
edge of the 9th bit of transmit clock pulse.
If ACKi is selected for the factor of DMA1 request, a DMA transfer can be activated by detection of an
acknowledge.
Jan 10, 2006
Transfer Clock
SDA Output
SDA Input
ACK and NACK
Page 213 of 390
2
C mode) and the SMD2 to SMD0
17. Serial Interface
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