MCF5481CVR166 Freescale Semiconductor, MCF5481CVR166 Datasheet - Page 21

• Manufacturer Part Number: MCF5481CVR166
• Description: IC MPU 32BIT COLDF 388-PBGA
• Manufacturer: Freescale Semiconductor
• Series: MCF548xr

Specifications of MCF5481CVR166

• Core Processor: Coldfire V4E
• Core Size: 32-Bit
• Speed: 166MHz
• Connectivity: CAN, EBI/EMI, Ethernet, I²C, SPI, UART/USART, USB
• Peripherals: DMA, PWM, WDT
• Number Of I /o: 99
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.43 V ~ 1.58 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MCF548x
• Core: ColdFire V4
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Maximum Clock Frequency: 83 MHz
• Operating Supply Voltage: 3 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• 3rd Party Development Tools: JLINK-CF-BDM26, EWCF
• Development Tools By Supplier: M5485EVBE, M5485EVBGHSE, M5484LITEKITE
• Minimum Operating Temperature: - 40 C
• Program Memory Size: 64KB
• Cpu Speed: 166MHz
• Embedded Interface Type: I2C, UART, DMA
• Digital Ic Case Style: BGA
• No. Of Pins: 388
• Rohs Compliant: Yes
• For Use With: M5485EVBGHSE - KIT DEV GHS FOR M5485EVBM5485EVBGHS - KIT DEV GHS FOR M5485EVBM5485BFEE - MODULE MCF5485 FIRE ENGINEM5485AFEE - MODULE MCF5485 FIRE ENGINEM5485AFE - MODULE MCF5485 FIRE ENGINEM5484GFEE - MODULE M5484 FIRE ENGINEM5484LITEKITE - KIT DEV FOR MCF548X FAMILY
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

10
The PCI bus on the MCF548x is PCI 2.2 compliant. The following timing numbers are mostly from the PCI 2.2 spec. Please
refer to the PCI 2.2 spec for a more detailed timing analysis.
Freescale Semiconductor
Num
SDCSn,SDWE,
P1
P2
P3
P4
P5
P6
PCI Bus
SDBA[1:0]
RAS, CAS
SDADDR,
SDCLK0
SDCLK1
SDCLK0
SDCLK1
Frequency of Operation
Clock Period (t
Address, Data, and Command (33< PCI ≤ 50 Mhz)—Input Setup (t
Address, Data, and Command (0 < PCI ≤ 33 Mhz)—Input Setup (t
Address, Data, and Command (33–50 Mhz)—Output Valid (t
Address, Data, and Command (0–33 Mhz) - Output Valid (t
PCI signals (0–50 Mhz) - Output Hold (t
SDDATA
SDDATA
SDDQS
SDDQS
CK
DD4
)
ROW
CMD
MCF548x ColdFire
Table 14. PCI Timing Specifications
Characteristic
DD1
Figure 17. DDR Read Timing
DD5
DH
)
®
COL
Microprocessor, Rev. 4
CL=2
CL=2.5
DV
DD2
DQS Read
DD10
DV
Preamble
)
)
DQS Read
DD3
Preamble
IS
IS
)
)
WD1 WD2 WD3 WD4
Min
3.0
7.0
25
20
—
—
0
WD1 WD2 WD3 WD4
DD9
Max
11.0
6.0
50
40
—
—
—
DQS Read
Postamble
MHz
Unit
ns
ns
ns
ns
ns
ns
DQS Read
Postamble
Notes
1
2
3
4
PCI Bus
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