ATTINY5-MAHR Atmel, ATTINY5-MAHR Datasheet - Page 86
![IC MCU AVR 512B FLASH 8UDFN](/photos/12/32/123206/8-udfn-8ma4_sml.jpg)
ATTINY5-MAHR
Manufacturer Part Number
ATTINY5-MAHR
Description
IC MCU AVR 512B FLASH 8UDFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY9-MAHR.pdf
(169 pages)
Specifications of ATTINY5-MAHR
Package / Case
8-UDFN Exposed Pad
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Operating Temperature
-40°C ~ 85°C
Speed
12MHz
Number Of I /o
4
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
32 x 8
Program Memory Size
512B (512 x 8)
Data Converters
A/D 4x8b
Oscillator Type
Internal
Peripherals
POR, PWM, WDT
Core Size
8-Bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
- Current page: 86 of 169
- Download datasheet (5Mb)
13.5
86
Prescaling and Conversion Timing
ATtiny4/5/9/10
Figure 13-2. ADC Auto Trigger Logic
Using the ADC interrupt flag as a trigger source makes the ADC start a new conversion as soon
as the ongoing conversion has finished. The ADC then operates in Free Running mode, con-
stantly sampling and updating the ADC data register. The first conversion must be started by
writing a logical one to bit ADSC bit in ADCSRA. In this mode the ADC will perform successive
conversions independently of whether the ADC Interrupt Flag, ADIF is cleared or not.
If Auto Triggering is enabled, single conversions can be started by writing ADSC in ADCSRA to
one. ADSC can also be used to determine if a conversion is in progress. The ADSC bit will be
read as one during a conversion, independently of how the conversion was started.
By default, the successive approximation circuitry requires an input clock frequency between 50
kHz and 200 kHz to get maximum resolution.
Figure 13-3. ADC Prescaler
The ADC module contains a prescaler, as illustrated in
an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is
set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ADC is
ADSC
SOURCE n
ADIF
SOURCE 1
.
.
.
.
ADEN
START
ADTS[2:0]
ADPS0
ADPS1
ADPS2
CK
DETECTOR
EDGE
Reset
ADATE
7-BIT ADC PRESCALER
ADC CLOCK SOURCE
Figure 13-3 on page
START
CONVERSION
PRESCALER
86, which generates
LOGIC
CLK
8127D–AVR–02/10
ADC
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