PIC16F716-E/SO Microchip Technology, PIC16F716-E/SO Datasheet - Page 23

• Manufacturer Part Number: PIC16F716-E/SO
• Description: IC PIC MCU FLASH 2KX14 18SOIC
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F716-E/SO

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 18-SOIC (7.5mm Width)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 13
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: RS- 232/USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 4-ch x 8-bit
• Data Rom Size: 128 B
• Height: 2.31 mm
• Length: 11.53 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 7.49 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: I3-DB16F716 - BOARD DAUGHTER ICEPIC3AC162054 - HEADER INTERFACE ICD2 16F716
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.2
PORTB is an 8-bit wide bidirectional port. The
corresponding data direction register is TRISB. Setting
a TRISB bit (= 1) will make the corresponding PORTB
pin an input (i.e., put the corresponding output driver in
a High-Impedance mode). Clearing a TRISB bit (= 0)
will make the corresponding PORTB pin an output (i.e.,
put the contents of the output latch on the selected pin).
EXAMPLE 3-2:
Each of the PORTB pins has a weak internal pull-up. A
single control bit can turn on all the pull-ups. This is
performed by clearing bit RBPU of the OPTION regis-
ter. The weak pull-up is automatically turned off when
the port pin is configured as an output. The pull-ups are
disabled on a Power-on Reset.
FIGURE 3-3:
© 2007 Microchip Technology Inc.
BCF
CLRF
BSF
MOVLW
MOVWF
RBPU
DATA
BUS
WR
PORT
Note
WR
TRIS
ECCPAS2: ECCP Auto-shutdown input
RB0/INT
(1)
1:
PORTB and the TRISB Register
STATUS, RP0
PORTB
STATUS, RP0
0xCF
TRISB
To enable weak pull-ups, set the appropriate TRIS
bit(s) and clear the RBPU bit (OPTION register).
RD TRIS
RD PORT
TRIS Latch
Data Latch
D
D
CK
CK
Q
Q
Schmitt Trigger
Buffer
INITIALIZING PORTB
BLOCK DIAGRAM OF
RB0/INT/ECCPAS2 PIN
Q
;select Bank 0
;Initialize PORTB by
;clearing output
;data latches
;Select Bank 1
;Value used to
;initialize data
;direction
;Set RB<3:0> as inputs
;RB<5:4> as outputs
;RB<7:6> as inputs
EN
D
TTL
Input
Buffer
V
P
DD
RD PORT
weak
pull-up
V
SS
V
DD
RB0/
INT/
ECCPAS2
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripherals override the TRIS bit to make a pin an
output, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (such as BSF, BCF, XORWF) with
TRISB as the destination should be avoided. The user
should refer to the corresponding peripheral section for
the correct TRIS bit settings.
Four of PORTB’s pins, RB<7:4>, have an interrupt-on-
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e., any RB<7:4> pin
configured as an output is excluded from the interrupt-
on-change comparison). The input pins, RB<7:4>, are
compared with the old value latched on the last read of
PORTB. The “mismatch” outputs of RB<7:4> are
OR’ed together to generate the RB Port Change
Interrupt with flag bit RBIF of the INTCON register.
This interrupt can wake the device from Sleep. The
user, in the Interrupt Service Routine, can clear the
interrupt in the following manner:
1.
2.
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt-on-change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt-on-change
feature. Polling of PORTB is not recommended while
using the interrupt-on-change feature.
Perform a read of PORTB to end the mismatch
condition.
Clear flag bit RBIF.
PIC16F716
DS41206B-page 21