ATTINY13A-SHR Atmel, ATTINY13A-SHR Datasheet - Page 16
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ATTINY13A-SHR
Manufacturer Part Number
ATTINY13A-SHR
Description
MCU AVR 1KB FLASH 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY13A-SHR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
1KB (512 x 16)
Program Memory Type
FLASH
Eeprom Size
64 x 8
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Package
8SOIC EIAJ
Device Core
AVR
Family Name
ATtiny
Maximum Speed
20 MHz
Operating Supply Voltage
2.5|3.3|5 V
Data Bus Width
8 Bit
Number Of Programmable I/os
6
Interface Type
SPI
On-chip Adc
4-chx10-bit
Number Of Timers
1
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY13A-SHR
Manufacturer:
Laird Technologies Inc
Quantity:
400 000
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5.2.1
5.3
16
EEPROM Data Memory
ATtiny13A
Data Memory Access Times
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, and the 64 bytes of internal data
SRAM in the ATtiny13A are all accessible through all these addressing modes. The Register
File is described in
Figure 5-2.
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
Figure 5-3.
The ATtiny13A contains 64 bytes of data EEPROM memory. It is organized as a separate data
space, in which single bytes can be read and written. The EEPROM has an endurance of at
least 100,000 write/erase cycles. The access between the EEPROM and the CPU is described
in the following, specifying the EEPROM Address Registers, the EEPROM Data Register, and
the EEPROM Control Register. For a detailed description of Serial data downloading to the
EEPROM, see
Data Memory Map
On-chip Data SRAM Access Cycles
page
Address
clk
Data
Data
“General Purpose Register File” on page
WR
CPU
RD
106.
Compute Address
64 I/O Registers
Data Memory
Internal SRAM
32 Registers
T1
(64 x 8)
Memory Access Instruction
Address valid
0x009F
0x0000 - 0x001F
0x0020 - 0x005F
0x0060
CPU
T2
cycles as described in
10.
Next Instruction
T3
Figure
8126E–AVR–07/10
5-3.
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