PIC12F635-E/P Microchip Technology, PIC12F635-E/P Datasheet - Page 121

• Manufacturer Part Number: PIC12F635-E/P
• Description: IC MCU FLASH 1KX14 8DIP
• Manufacturer: Microchip Technology
• Series: PIC® 12Fr

Specifications of PIC12F635-E/P

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Core Processor: PIC
• Speed: 20MHz
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 5
• Program Memory Type: FLASH
• Eeprom Size: 128 x 8
• Ram Size: 64 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 8-DIP (0.300", 7.62mm)
• Controller Family/series: PIC12
• No. Of I/o's: 6
• Eeprom Memory Size: 128Byte
• Ram Memory Size: 64Byte
• Cpu Speed: 20MHz
• No. Of Timers: 2
• Processor Series: PIC12F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 64 B
• Interface Type: RS- 232, SPI, USB
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 6
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029, DV164101, DM163014
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DM163029 - BOARD PICDEM FOR MECHATRONICSAC162057 - MPLAB ICD 2 HEADER 14DIPACICE0201 - MPLABICE 8P 300 MIL ADAPTER
• Data Converters: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

FIGURE 11-17:
© 2007 Microchip Technology Inc.
LFDATA/RSSI/
MCU SPI Write Details:
1.
2.
3.
4.
5.
6.
7.
CCLK/SDIO
ALERT
SCLK/
Drive the AFE’s open collector ALERT output low.
•
Drop CS.
•
•
Change LFDATA/RSSI/CCLK/SDIO connected pin to output.
•
Clock in 16-bit SPI Write sequence - command, address, data and parity bit.
•
Change LFDATA/RSSI/CCLK/SDIO connected pin to input.
Raise CS to complete the SPI Write.
Change SCLK/ALERT back to input.
CS
To ensure no false clocks occur when CS drops.
AFE SCLK/ALERT becomes SCLK input.
LFDATA/RSSI/CCLK/SDIO becomes SDI input.
Driving SPI data.
Command, address, data and parity bit.
(output)
ALERT
LFDATA
(output)
1
SPI WRITE SEQUENCE
(input)
2
SCLK
(input)
T
CSSC
SDI
T
3
SU
MSb
T
HD
4
16 Clocks for Write Command, Address and Data
PIC12F635/PIC16F636/639
T
HI
1/F
SCLK
T
LO
LSb
T
SCCS
5
6
T
LFDATA
(output)
CS
1
(output)
DS41232D-page 119
ALERT
T
7
CSH
T
CS
0