PIC12HV615-I/P Microchip Technology, PIC12HV615-I/P Datasheet - Page 108
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PIC12HV615-I/P
Manufacturer Part Number
PIC12HV615-I/P
Description
IC PIC MCU FLASH 1KX14 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Fr
Datasheets
1.PIC12F609T-ISN.pdf
(212 pages)
2.PIC12F609T-ISN.pdf
(8 pages)
3.PIC12F609T-ISN.pdf
(26 pages)
4.PIC16F616T-ISL.pdf
(4 pages)
5.PIC16F616T-ISL.pdf
(8 pages)
6.PIC12F615-ESN.pdf
(168 pages)
Specifications of PIC12HV615-I/P
Program Memory Type
FLASH
Program Memory Size
1.75KB (1K x 14)
Package / Case
8-DIP (0.300", 7.62mm)
Core Processor
PIC
Core Size
8-Bit
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
5
Ram Size
64 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC12H
Core
PIC
Data Bus Width
8 bit
Data Ram Size
64 B
Interface Type
RS-232/USB
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
5
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
4-ch x 10-bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
AC162083 - HEADER MPLAB ICD2 PIC16F616 8/14AC162059 - HEADER INTRFC MPLAB ICD2 8/14PINAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12HV615-I/P
Manufacturer:
MIC
Quantity:
3 580
Part Number:
PIC12HV615-I/P
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
PIC12F609/615/12HV609/615
11.5
During an interrupt, only the return PC value is saved
on the stack. Typically, users may wish to save key
registers during an interrupt (e.g., W and STATUS
registers). This must be implemented in software.
Temporary
STATUS_TEMP should be placed in the last 16 bytes
of GPR (see Figure 2-2). These 16 locations are
common to all banks and do not require banking. This
makes context save and restore operations simpler.
The code shown in Example 11-1 can be used to:
• Store the W register
• Store the STATUS register
• Execute the ISR code
• Restore the Status (and Bank Select Bit register)
• Restore the W register
EXAMPLE 11-1:
11.6
The Watchdog Timer is a free running, on-chip RC
oscillator, which requires no external components. This
RC oscillator is separate from the external RC oscillator
of the CLKIN pin and INTOSC. That means that the
WDT will run, even if the clock on the OSC1 and OSC2
pins of the device has been stopped (for example, by
execution of a SLEEP instruction). During normal oper-
ation, a WDT time out generates a device Reset. If the
device is in Sleep mode, a WDT time out causes the
device to wake-up and continue with normal operation.
The WDT can be permanently disabled by program-
ming
(Section 11.1 “Configuration Bits”).
DS41302A-page 106
Note:
MOVWF
SWAPF
MOVWF
:
:(ISR)
:
SWAPF
MOVWF
SWAPF
SWAPF
the
Context Saving During Interrupts
Watchdog Timer (WDT)
The PIC12F609/615/12HV609/615 does
not require saving the PCLATH. However,
if computed GOTOs are used in both the
ISR and the main code, the PCLATH must
be saved and restored in the ISR.
Configuration
holding
W_TEMP
STATUS,W
STATUS_TEMP
STATUS_TEMP,W
STATUS
W_TEMP,F
W_TEMP,W
SAVING STATUS AND W REGISTERS IN RAM
registers
bit,
WDTE,
;Copy W to TEMP register
;Swap status to be saved into W
;Swaps are used because they do not affect the status bits
;Save status to bank zero STATUS_TEMP register
;Insert user code here
;Swap STATUS_TEMP register into W
;(sets bank to original state)
;Move W into STATUS register
;Swap W_TEMP
;Swap W_TEMP into W
W_TEMP
as
clear
and
Preliminary
11.6.1
The WDT has a nominal time-out period of 18 ms (with
no prescaler). The time-out periods vary with
temperature, V
part (see DC specs). If longer time-out periods are
desired, a prescaler with a division ratio of up to 1:128
can be assigned to the WDT under software control by
writing to the OPTION register. Thus, time-out periods
up to 2.3 seconds can be realized.
The CLRWDT and SLEEP instructions clear the WDT
and the prescaler, if assigned to the WDT, and prevent
it from timing out and generating a device Reset.
The TO bit in the STATUS register will be cleared upon
a Watchdog Timer time out.
WDT PERIOD
DD
and process variations from part to
© 2006 Microchip Technology Inc.