ATTINY45V-10SH Atmel, ATTINY45V-10SH Datasheet - Page 57
![IC MCU AVR 4KB FLASH 20MHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY45V-10SH
Manufacturer Part Number
ATTINY45V-10SH
Description
IC MCU AVR 4KB FLASH 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY45V-10SH
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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10.2.2
10.2.3
10.2.4
2586M–AVR–07/10
Toggling the Pin
Switching Between Input and Output
Reading the Pin Value
Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn.
Note that the SBI instruction can be used to toggle one single bit in a port.
When switching between tri-state ({DDxn, PORTxn} = 0b00) and output high ({DDxn, PORTxn}
= 0b11), an intermediate state with either pull-up enabled {DDxn, PORTxn} = 0b01) or output
low ({DDxn, PORTxn} = 0b10) must occur. Normally, the pull-up enabled state is fully accept-
able, as a high-impedant environment will not notice the difference between a strong high driver
and a pull-up. If this is not the case, the PUD bit in the MCUCR Register can be set to disable all
pull-ups in all ports.
Switching between input with pull-up and output low generates the same problem. The user
must use either the tri-state ({DDxn, PORTxn} = 0b00) or the output high state ({DDxn, PORTxn}
= 0b10) as an intermediate step.
Table 10-1
Table 10-1.
Independent of the setting of Data Direction bit DDxn, the port pin can be read through the
PINxn Register bit. As shown in
stitute a synchronizer. This is needed to avoid metastability if the physical pin changes value
near the edge of the internal clock, but it also introduces a delay.
gram of the synchronization when reading an externally applied pin value. The maximum and
minimum propagation delays are denoted t
Figure 10-3. Synchronization when Reading an Externally Applied Pin value
DDxn
0
0
0
1
1
PORTxn
summarizes the control signals for the pin value.
INSTRUCTIONS
0
1
1
0
1
Port Pin Configurations
SYSTEM CLK
SYNC LATCH
PINxn
(in MCUCR)
r17
PUD
X
X
X
0
1
Figure
XXX
Output
Output
Input
Input
Input
10-2, the PINxn Register bit and the preceding latch con-
I/O
pd,max
t
pd, max
Pull-up
and t
0x00
Yes
No
No
No
No
XXX
pd,min
t
pd, min
Comment
Tri-state (Hi-Z)
Pxn will source current if ext. pulled low.
Tri-state (Hi-Z)
Output Low (Sink)
Output High (Source)
respectively.
in r17, PINx
Figure 10-3
shows a timing dia-
0xFF
57
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