ATTINY45V-10SH Atmel, ATTINY45V-10SH Datasheet - Page 78
![IC MCU AVR 4KB FLASH 20MHZ 8SOIC](/photos/6/50/65032/453-8-soic_sml.jpg)
ATTINY45V-10SH
Manufacturer Part Number
ATTINY45V-10SH
Description
IC MCU AVR 4KB FLASH 20MHZ 8SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY45V-10SH
Core Processor
AVR
Core Size
8-Bit
Speed
10MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
6
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 4x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Processor Series
ATtiny
Core
AVR
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI, USI
Maximum Clock Frequency
10 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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11.8
78
Timer/Counter Timing Diagrams
ATtiny25/45/85
not available for the OC0B pin (See
visible on the port pin if the data direction for the port pin is set as output. The PWM waveform is
generated by clearing (or setting) the OC0x Register at the Compare Match between OCR0x
and TCNT0 when the counter increments, and setting (or clearing) the OC0x Register at Com-
pare Match between OCR0x and TCNT0 when the counter decrements. The PWM frequency for
the output when using phase correct PWM can be calculated by the following equation:
The N variable represents the prescale factor (1, 8, 64, 256, or 1024).
The extreme values for the OCR0A Register represent special cases when generating a PWM
waveform output in the phase correct PWM mode. If the OCR0A is set equal to BOTTOM, the
output will be continuously low and if set equal to MAX the output will be continuously high for
non-inverted PWM mode. For inverted PWM the output will have the opposite logic values.
At the very start of period 2 in
there is no Compare Match. The point of this transition is to guaratee symmetry around BOT-
TOM. There are two cases that give a transition without Compare Match, as follows:
The Timer/Counter is a synchronous design and the timer clock (clk
clock enable signal in the following figures. The figures include information on when Interrupt
Flags are set.
shows the count sequence close to the MAX value in all modes other than phase correct PWM
mode.
Figure 11-10. Timer/Counter Timing Diagram, no Prescaling
Figure 11-11
TCNTn
(clk
TOVn
• OCR0A changes its value from MAX, like in
• The timer starts counting from a value higher than the one in OCR0A, and for that reason
clk
clk
OCn pin value is the same as the result of a down-counting Compare Match. To ensure
symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-
counting Compare Match.
misses the Compare Match and hence the OCn change that would have happened on the
way up.
I/O
I/O
Tn
/1)
shows the same timing data, but with the prescaler enabled.
Figure 11-10
MAX - 1
contains timing data for basic Timer/Counter operation. The figure
Figure 11-9
Table 11-4 on page
f
OCnxPCPWM
OCn has a transition from high to low even though
MAX
Figure
=
------------------
N 510
f
clk_I/O
11-9. When the OCR0A value is MAX the
⋅
81). The actual OC0x value will only be
BOTTOM
T0
) is therefore shown as a
BOTTOM + 1
2586M–AVR–07/10
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