PIC16F688-E/ST Microchip Technology, PIC16F688-E/ST Datasheet - Page 435

• Manufacturer Part Number: PIC16F688-E/ST
• Description: IC MCU FLASH 4KX14 14TSSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F688-E/ST

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 14-TSSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 12
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 12
• Number Of Timers: 2
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8-ch x 10-bit
• Data Rom Size: 256 B
• Height: 0.9 mm
• Length: 5 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 4.4 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT14SS-1 - SOCKET TRANSITION 14DIP/14SSOPAC162061 - HEADER INTRFC MPLAB ICD2 20PINAC162056 - HEADER INTERFACE ICD2 16F688
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Section 23. 10-bit A/D Converter
23.7.2
A/D Result Registers
The ADRESH:ADRESL register pair is the location where the 10-bit A/D result is loaded at the
completion of the A/D conversion. This register pair is 16-bits wide. The A/D module gives the
flexibility to left or right justify the 10-bit result in the 16-bit result register. The A/D Format Select
bit (ADFM) controls this justification.
Figure 23-6
shows the operation of the A/D result justifica-
tion. The extra bits are loaded with ‘0’s’. When an A/D result will not overwrite these locations (A/D
disable), these registers may be used as two general purpose 8-bit registers.
Figure 23-6: A/D Result Justification
10-Bit Result
ADFM = 0
ADFM = 1
0
7
7
2 1 0 7
0 7 6 5
0
RESULT
RESULT
0000 00
0000 00
ADRESH
ADRESH
ADRESL
ADRESL
10-bits
10-bits
23
Left Justified
Right Justified
Preliminary
1997 Microchip Technology Inc.
DS31023A-page 23-13