PIC12CE519-04E/SM Microchip Technology, PIC12CE519-04E/SM Datasheet - Page 288
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC12CE519-04E/SM
Manufacturer Part Number
PIC12CE519-04E/SM
Description
IC MCU OTP 1KX12 W/EE 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12C508A-04SM.pdf
(113 pages)
3.PIC12C508A-04SM.pdf
(4 pages)
4.PIC12CE518-04SM.pdf
(16 pages)
Specifications of PIC12CE519-04E/SM
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.5KB (1K x 12)
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE519-04E/SM
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC16F688T-ISL PDF datasheet
- PIC12C508A-04SM PDF datasheet #2
- PIC12C508A-04SM PDF datasheet #3
- PIC12CE518-04SM PDF datasheet #4
- Current page: 288 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
17.3.4
DS31017A-page 17-12
Master Mode
The master can initiate the data transfer at any time because it controls the SCK. The master
determines when the slave (Processor 2,
tocol.
In master mode the data is transmitted/received as soon as the SSPBUF register is written to. If
the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed
clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately set). This could be useful in receiver appli-
cations as a “line activity monitor” mode.
The clock polarity is selected by appropriately programming the CKP bit (SSPCON1<4>). This
then would give waveforms for SPI communication as shown in
Figure 17-9
user programmable to be one of the following:
• F
• F
• F
• Timer2 output/2
This allows a maximum data rate (at 20 MHz) of 8.25 Mbps.
Figure 17-6
valid before there is a clock edge on SCK. The change of the input sample is shown based on
the state of the SMP bit. The time when the SSPBUF is loaded with the received data is shown.
OSC
OSC
OSC
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
where the MSb is transmitted first. In master mode, the SPI clock rate (bit rate) is
Shows the waveforms for master mode. When the CKE bit is set, the SDO data is
CY
)
CY
CY
)
)
Preliminary
Figure
17-5) is to broadcast data by the software pro-
Figure
1997 Microchip Technology Inc.
17-6,
Figure
17-8, and
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