PIC12CE519-04E/SM Microchip Technology, PIC12CE519-04E/SM Datasheet - Page 348
![no-image](/images/manufacturer_photos/0/4/439/microchip_technology_sml.jpg)
PIC12CE519-04E/SM
Manufacturer Part Number
PIC12CE519-04E/SM
Description
IC MCU OTP 1KX12 W/EE 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC16F688T-ISL.pdf
(688 pages)
2.PIC12C508A-04SM.pdf
(113 pages)
3.PIC12C508A-04SM.pdf
(4 pages)
4.PIC12CE518-04SM.pdf
(16 pages)
Specifications of PIC12CE519-04E/SM
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.5KB (1K x 12)
Program Memory Type
OTP
Eeprom Size
16 x 8
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOIC309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Connectivity
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12CE519-04E/SM
Manufacturer:
MICROCHIP
Quantity:
12 000
- PIC16F688T-ISL PDF datasheet
- PIC12C508A-04SM PDF datasheet #2
- PIC12C508A-04SM PDF datasheet #3
- PIC12CE518-04SM PDF datasheet #4
- Current page: 348 of 688
- Download datasheet (3Mb)
PICmicro MID-RANGE MCU FAMILY
DS31018A-page 18-12
RX (pin)
Rcv shift
reg
Rcv buffer reg
Read Rcv
buffer reg
RCREG
RCIF
(interrupt flag)
OERR bit
CREN
Note: This timing diagram shows three words appearing on the RX input. The RCREG (receive buffer) is read after the third word,
causing the OERR (overrun) bit to be set.
Start
Steps to follow when setting up an Asynchronous Reception:
1.
2.
3.
4.
5.
6.
7.
8.
9.
Figure 18-5:
bit
Initialize the SPBRG register for the appropriate baud rate. If a high speed baud rate is
desired, set bit BRGH. (Subsection
Enable the asynchronous serial port by clearing the SYNC bit, and setting the SPEN bit.
If interrupts are desired, then set the RCIE, GIE and PEIE bits.
If 9-bit reception is desired, then set the RX9 bit.
Enable the reception by setting the CREN bit.
The RCIF flag bit will be set when reception is complete and an interrupt will be generated
if the RCIE bit was set.
Read the RCSTA register to get the ninth bit (if enabled) and determine if any error
occurred during reception.
Read the 8-bit received data by reading the RCREG register.
If any error occurred, clear the error by clearing the CREN bit.
bit0
bit1
Asynchronous Reception
bit7/8
Stop
bit
WORD 1
RCREG
Start
bit
18.3 “USART Baud Rate Generator (BRG)”
bit0
bit7/8
WORD 2
RCREG
Stop
bit
Start
bit
1997 Microchip Technology Inc.
bit7/8
Stop
bit
).
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