PIC16HV785-I/SO Microchip Technology, PIC16HV785-I/SO Datasheet - Page 34

IC PIC MCU FLASH 2KX14 20SOIC

PIC16HV785-I/SO

Manufacturer Part Number
PIC16HV785-I/SO
Description
IC PIC MCU FLASH 2KX14 20SOIC
Manufacturer
Microchip Technology
Series
PIC® 16Fr

Specifications of PIC16HV785-I/SO

Core Size
8-Bit
Program Memory Size
3.5KB (2K x 14)
Oscillator Type
Internal
Core Processor
PIC
Speed
20MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
17
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2 V ~ 5.5 V
Data Converters
A/D 14x10b
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Controller Family/series
PIC16HV
No. Of I/o's
18
Eeprom Memory Size
256Byte
Ram Memory Size
128Byte
Cpu Speed
20MHz
Processor Series
PIC16H
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
RS- 232, USB
Maximum Clock Frequency
32 MHz
Number Of Programmable I/os
18
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DV164120, DM163029
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 14 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT20SO1-1 - SOCKET TRANS ICE 20DIP TO 20SOICAC162060 - HEADER INTRFC MPLAB ICD2 20PINAC164039 - MODULE SKT PROMATE II 20DIP/SOIC
Connectivity
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC16HV785-I/SO
Manufacturer:
MICROCHIP
Quantity:
12 000
PIC16F785/HV785
3.7.1
The Fail-Safe condition is cleared after a Reset, the
execution of a SLEEP instruction, or a modification of
the SCS bit. While in Fail-Safe condition, the
PIC16F785/HV785 uses the internal oscillator as the
system clock source. The IRCF bits (OSCCON<6:4>)
can be modified to adjust the internal oscillator
frequency without exiting the Fail-Safe condition.
The Fail-Safe condition must be cleared before the
OSFIF flag can be cleared.
FIGURE 3-9:
3.7.2
The FSCM is designed to detect oscillator failure at any
point after the device has exited a Reset or Sleep
condition and the Oscillator Start-up Timer (OST) has
expired. If the external clock is EC or RC mode,
monitoring will begin immediately following these
events.
For LP, XT or HS mode, the external oscillator may
require a start-up time considerably longer than the
FSCM sample clock time; a false clock failure may be
detected (see Figure 3-9). To prevent this, the internal
oscillator is automatically configured as the system
clock and functions until the external clock is stable (the
OST has timed out). This is identical to Two-Speed
Start-up mode. Once the external oscillator is stable,
the LFINTOSC returns to its role as the FSCM source.
DS41249D-page 32
Note:
Sample Clock
Note:
CM Output
OSCFIF
System
FAIL-SAFE CONDITION CLEARING
RESET OR WAKE-UP FROM SLEEP
Due to the wide range of oscillator start-up
times, the Fail-Safe circuit is not active
during oscillator start-up (i.e., after exiting
Reset or Sleep). After an appropriate
amount of time, the user should check the
OSTS bit (OSCCON<3>) to verify the
oscillator start-up and system clock
switchover has successfully completed.
Output
Clock
(Q)
The system clock is normally at a much higher frequency than the sample clock. The relative frequencies in
this example have been chosen for clarity.
FSCM TIMING DIAGRAM
CM Test
Preliminary
CM Test
Oscillator
Failure
© 2006 Microchip Technology Inc.
Detected
Failure
CM Test

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