ATTINY461-20SUR Atmel, ATTINY461-20SUR Datasheet - Page 139

• Manufacturer Part Number: ATTINY461-20SUR
• Description: MCU AVR 4KB FLASH 20MHZ 20SOIC
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY461-20SUR

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: USI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Program Memory Size: 4KB (2K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 11x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

14.2
14.2.1
2588E–AVR–08/10
Register Description
ACSRA – Analog Comparator Control and Status Register A
• Bit 7 – ACD: Analog Comparator Disable
When this bit is written logic one, the power to the analog comparator is switched off. This bit
can be set at any time to turn off the analog comparator, thus reducing power consumption in
Active and Idle mode. When changing the ACD bit, the analog comparator Interrupt must be dis-
abled by clearing the ACIE bit in ACSRA. Otherwise an interrupt can occur when the bit is
changed.
• Bit 6 – ACBG: Analog Comparator Bandgap Select
When this bit is set an internal 1.1V reference voltage replaces the positive input to the analog
comparator. The selection of the internal voltage reference is done by writing the REFS2:0 bits
in ADCSRB and ADMUX registers. When this bit is cleared, AIN0, AIN1 or AIN2 depending on
the ACM2:0 bits is applied to the positive input of the analog comparator.
• Bit 5 – ACO: Analog Comparator Output
Enables output of analog comparator. The output of the analog comparator is synchronized and
then directly connected to ACO. The synchronization introduces a delay of 1 - 2 clock cycles.
• Bit 4 – ACI: Analog Comparator Interrupt Flag
This bit is set by hardware when a comparator output event triggers the interrupt mode defined
by ACIS1 and ACIS0. The analog comparator interrupt routine is executed if the ACIE bit is set
and the I-bit in SREG is set. ACI is cleared by hardware when executing the corresponding inter-
rupt handling vector. Alternatively, ACI is cleared by writing a logic one to the flag.
• Bit 3 – ACIE: Analog Comparator Interrupt Enable
When the ACIE bit is written logic one and the I-bit in the status register is set, the analog com-
parator interrupt is activated. When written logic zero, the interrupt is disabled.
• Bit 2 – ACME: Analog Comparator Multiplexer Enable
When this bit is written logic one and the ADC is switched off (ADEN in ADCSRA is zero), the
ADC multiplexer selects the negative input to the analog comparator. When this bit is written
logic zero, AIN1 is applied to the negative input of the analog comparator. For a detailed descrip-
tion of this bit, see
Bit
0x08 (0x28)
Read/Write
Initial Value
ACD
R/W
7
0
Table 14-1 on page
ACBG
R/W
6
0
ACO
N/A
R
5
137.
R/W
ACI
4
0
ACIE
R/W
3
0
ACME
R/W
2
0
ACIS1
R/W
1
0
ACIS0
R/W
0
0
ACSRA
139