AT90PWM2B-16SU Atmel, AT90PWM2B-16SU Datasheet - Page 154
AT90PWM2B-16SU
Manufacturer Part Number
AT90PWM2B-16SU
Description
IC MCU AVR RISC 8K FLASH 24-SOIC
Manufacturer
Atmel
Series
AVR® 90PWM Lightingr
Datasheet
1.AT90PWM3B-16SU.pdf
(361 pages)
Specifications of AT90PWM2B-16SU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
19
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 105°C
Package / Case
24-SOIC (7.5mm Width)
Processor Series
AT90PWMx
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
SPI, USART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
19
Number Of Timers
2
Maximum Operating Temperature
+ 105 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, ATAVRFBKIT, ATAVRISP2
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
On-chip Dac
10 bit, 1 Channel
For Use With
ATSTK600-SOIC - STK600 SOCKET/ADAPTER FOR SOIC770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRFBKIT - KIT DEMO BALLAST FOR AT90PWM2ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK520 - ADAPTER KIT FOR 90PWM
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AT90PWM2B-16SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
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16.18 PSC Input Mode 14: Fixed Frequency Edge Retrigger PSC and Disactivate Output
154
PSCOUTn0
PSCOUTn1
PSCn Input A
AT90PWM2/3/2B/3B
PSCn Input B
PSCOUTn0
PSCOUTn1
DT0
DT0
Figure 16-33. PSC behaviour versus PSCn Input A in Mode 9
The output frequency is not modified by the occurence of significative edge of retriggering input.
Only the output is disactivated when significative edge on retriggering input occurs.
Note: In this mode the output of the PSC becomes active during the next ramp even if the Retrig-
ger/Fault input is actve. Only the significative edge of Retrigger/Fault input is taken into account.
Figure 16-34. PSC behaviour versus PSCn Input B in Mode 9
The retrigger event is taken into account only if it occurs during the corresponding On-Time.
OT0
OT0
DT1
DT1
OT1
OT1
DT0
DT0
OT0
OT0
DT1
DT1
OT1
OT1
DT0
DT0
OT0
OT0
DT1
DT1
4317J–AVR–08/10
OT1
OT1
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