PIC16LF648A-I/P Microchip Technology, PIC16LF648A-I/P Datasheet - Page 109

• Manufacturer Part Number: PIC16LF648A-I/P
• Description: IC PIC MCU FLASH 4KX14 18DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16LF648A-I/P

• Program Memory Type: FLASH
• Program Memory Size: 7KB (4K x 14)
• Package / Case: 18-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16LF
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: SCI/USART
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, DM163014, DM164120-4
• Minimum Operating Temperature: - 40 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

FIGURE 14-16:
TABLE 14-9:
14.8
The Power-down mode is entered by executing a
SLEEP
If enabled, the Watchdog Timer will be cleared but
keeps running, the PD bit in the Status Register is
cleared, the TO bit is set, and the oscillator driver is
turned off. The I/O ports maintain the status they
had, before
or hi-impedance).
 2004 Microchip Technology Inc.
Legend:
81h, 181h
Address
Note:
2007h
Note:
instruction.
Power-Down Mode (Sleep)
x = unknown, u = unchanged, - = unimplemented read as ‘0’, q = value depends upon condition.
Shaded cells are not used by the Watchdog Timer.
SLEEP
OPTION
Config.
Name
bits
T0SE, T0CS, PSA, PS0-PS2 are bits in the OPTION register.
SUMMARY OF WATCHDOG TIMER REGISTERS
was executed (driving high, low,
Enable Bit
Watchdog
WATCHDOG TIMER BLOCK DIAGRAM
RBPU
Bit 7
Timer
WDT
LVP
From TMR0 Clock Source
INTEDG
BOREN
(Figure 6-1)
Bit 6
MCLRE
T0CS
Bit 5
PSA
0
1
M
U
X
FOSC2
T0SE
Bit 4
Preliminary
PIC16F627A/628A/648A
PWRTE
Bit 3
PSA
WDT POSTSCALER/
TMR0 PRESCALER
For lowest current consumption in this mode, all I/O
pins should be either at V
circuitry drawing current from the I/O pin and the
comparators, and V
that are hi-impedance inputs should be pulled high or
low externally to avoid switching currents caused by
floating inputs. The T0CKI input should also be at V
or
contribution from on chip pull-ups on PORTB should be
considered.
The MCLR pin must be at a logic high level (V
0
Time out
Note:
MUX
WDT
8 to 1 MUX
V
WDTE
Bit 2
PS2
SS
1
8
for
It should be noted that a Reset generated
by a WDT time out does not drive MCLR
pin low.
FOSC1
Bit 1
PS1
lowest
PSA
3
(Figure 6-1)
REF
PS<2:0>
To TMR0
FOSC0
Bit 0
PS0
should be disabled. I/O pins
current
DD
, or V
uuuu uuuu uuuu uuuu
1111 1111 1111 1111
POR Reset
Value on
SS
consumption.
DS40044B-page 107
, with no external
Value on all
Resets
IHMC
other
The
).
DD