PIC16C712-04/SS Microchip Technology, PIC16C712-04/SS Datasheet - Page 24

• Manufacturer Part Number: PIC16C712-04/SS
• Description: IC MCU OTP 1KX14 A/D PWM 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 16Cr

Specifications of PIC16C712-04/SS

• Core Size: 8-Bit
• Program Memory Size: 1.75KB (1K x 14)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 4MHz
• Number Of I /o: 13
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 20-SSOP
• Controller Family/series: PIC16C
• No. Of I/o's: 13
• Ram Memory Size: 128Byte
• Cpu Speed: 4MHz
• No. Of Timers: 3
• Processor Series: PIC16C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 13
• Number Of Timers: 3 bit
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• On-chip Adc: 4 bit
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 309-1016 - ADAPTER 20-SSOP TO 18-DIP
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

PIC16C712/716
PORTB pins RB3:RB1 are multiplexed with several
peripheral functions (Table 3-3). PORTB pins RB3:RB0
have Schmitt Trigger input buffers.
When enabling peripheral functions, care should be
taken in defining TRIS bits for each PORTB pin. Some
peripherals override the TRIS bit to make a pin an out-
put, while other peripherals override the TRIS bit to
make a pin an input. Since the TRIS bit override is in
effect while the peripheral is enabled, read-modify-
write instructions (BSF, BCF, XORWF) with TRISB as
destination should be avoided. The user should refer to
the corresponding peripheral section for the correct
TRIS bit settings.
Four of PORTB’s pins, RB7:RB4, have an interrupt on
change feature. Only pins configured as inputs can
cause this interrupt to occur (i.e. any RB7:RB4 pin con-
figured as an output is excluded from the interrupt on
change comparison). The input pins, RB7:RB4, are
compared with the old value latched on the last read of
FIGURE 3-4:
DS41106A-page 24
WR TRISB
T1OSCEN
TMR1CS
Note 1: To enable weak pull-ups, set the appropriate TRIS bit(s) and clear the RBPU bit (OPTION_REG<7>).
RD
DATACCP
WR
DATACCP
WR
TRISCCP
WR
PORTB
BLOCK DIAGRAM OF RB1/T1OSO/T1CKI PIN
DATA BUS
RD PORTB
DATACCP<0>
TRISB<1>
TRISCCP<0>
PORTB<1>
D
D
D
D
CK
CK
CK
CK
Q
Q
Q
Q
Q
Q
Q
Q
RBPU
T1OSCEN
T1CS
(1)
T1CLKIN
Preliminary
1
0
TTL Buffer
1
0
1
0
PORTB. The “mismatch” outputs of RB7:RB4 are
OR’ed together to generate the RB Port Change Inter-
rupt with flag bit RBIF (INTCON<0>).
This interrupt can wake the device from SLEEP. The
user, in the interrupt service routine, can clear the inter-
rupt in the following manner:
a)
b)
A mismatch condition will continue to set flag bit RBIF.
Reading PORTB will end the mismatch condition and
allow flag bit RBIF to be cleared.
The interrupt on change feature is recommended for
wake-up on key depression operation and operations
where PORTB is only used for the interrupt on change
feature. Polling of PORTB is not recommended while
using the interrupt on change feature.
Any read or write of PORTB will end the mis-
match condition.
Clear flag bit RBIF.
ST
Buffer
V
P
DD
weak
pull-up
V
SS
V
DD
1999 Microchip Technology Inc.
RB1/T1OSO/T1CKI