PIC12LC671-04I/P Microchip Technology, PIC12LC671-04I/P Datasheet - Page 12
![IC MCU OTP 1KX14 LV A/D 8DIP](/photos/16/0/160065/8-pdip-angled-300dpi-lyrd_sml.jpg)
PIC12LC671-04I/P
Manufacturer Part Number
PIC12LC671-04I/P
Description
IC MCU OTP 1KX14 LV A/D 8DIP
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Specifications of PIC12LC671-04I/P
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Size
1.75KB (1K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
8-DIP (0.300", 7.62mm)
Processor Series
PIC12LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
8
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
8
For Use With
309-1051 - ADAPTER 8-DIP BD W/2 SO PLUGS
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
PIC12C67X
FIGURE 4-2:
DS30561B-page 12
Note 1: Not a physical register.
Address
File
0Ch
0Dh
1Ch
1Dh
0Ah
0Bh
0Eh
1Ah
1Bh
1Eh
0Fh
1Fh
70h
7Fh
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
10h
12h
13h
14h
15h
16h
17h
18h
19h
20h
11h
Unimplemented data memory locations, read
as ’0’.
ADCON0
PCLATH
STATUS
INTCON
ADRES
INDF
Bank 0
Purpose
Register
TMR0
GPIO
General
PIR1
FSR
PCL
PIC12C67X REGISTER FILE
MAP
(1)
ADCON1
in Bank 0
PCLATH
OPTION
STATUS
INTCON
OSCCAL
Purpose
Register
General
Mapped
INDF
Bank 1
PCON
TRIS
PIE1
FSR
PCL
(1)
Address
EFh
80h
81h
82h
83h
84h
85h
86h
87h
88h
89h
8Ah
8Bh
8Ch
8Dh
8Eh
8Fh
90h
91h
92h
93h
94h
95h
96h
97h
98h
99h
9Ah
9Bh
9Ch
9Dh
9Eh
9Fh
A0h
BFh
C0h
F0h
FFh
File
4.2.2
The Special Function Registers are registers used by
the CPU and Peripheral Modules for controlling the
desired operation of the device. These registers are
implemented as static RAM.
The Special Function Registers can be classified into
two sets (core and peripheral). Those registers associ-
ated with the “core” functions are described in this sec-
tion, and those related to the operation of the peripheral
features are described in the section of that peripheral
feature.
SPECIAL FUNCTION REGISTERS
1999 Microchip Technology Inc.