PIC12LC671-04I/SM Microchip Technology, PIC12LC671-04I/SM Datasheet - Page 13

• Manufacturer Part Number: PIC12LC671-04I/SM
• Description: IC MCU OTP 1KX14 LV A/D 8-SOIJ
• Manufacturer: Microchip Technology
• Series: PIC® 12Cr

Specifications of PIC12LC671-04I/SM

• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 4MHz
• Peripherals: POR, WDT
• Number Of I /o: 5
• Program Memory Size: 1.75KB (1K x 14)
• Program Memory Type: OTP
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 4x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
• Processor Series: PIC12LC
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Maximum Clock Frequency: 4 MHz
• Number Of Programmable I/os: 5
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Connectivity: -
• Lead Free Status / Rohs Status: Details

TABLE 4-1:
00h
01h
02h
03h
04h
05h
06h
07h
08h
09h
0Ah
0Bh
0Ch
0Dh
0Eh
0Fh
10h
11h
12h
13h
14h
15h
16h
17h
18h
19h
1Ah
1Bh
1Ch
1Dh
1Eh
1Fh
Legend: x = unknown, u = unchanged, q = value depends on condition, - = unimplemented read as ’0’.
Note 1: These registers can be addressed from either bank.
Address
Bank 0
1999 Microchip Technology Inc.
(1)
(1)
(1)
(1)
(1,2)
(1)
2: The upper byte of the program counter is not directly accessible. PCLATH is a holding register for the PC<12:8> whose con-
3: Other (non power-up) resets include external reset through MCLR and Watchdog Timer Reset.
4: The IRP and RP1 bits are reserved on the PIC12C67X; always maintain these bits clear.
5: The SCL (GP7) and SDA (GP6) bits are unimplemented on the PIC12C671/672 and read as ’0’.
INDF
TMR0
PCL
STATUS
FSR
GPIO
PCLATH
INTCON
PIR1
ADRES
ADCON0
Shaded locations are unimplemented, read as ‘0’.
tents are transferred to the upper byte of the program counter.
Name
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
PIC12C67X SPECIAL FUNCTION REGISTER SUMMARY
Addressing this location uses contents of FSR to address data memory (not a physical register)
Timer0 module’s register
Program Counter's (PC) Least Significant Byte
Indirect data memory address pointer
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
Unimplemented
A/D Result Register
ADCS1
SCL
IRP
Bit 7
GIE
—
—
(4)
(5)
ADCS0
RP1
SDA
PEIE
ADIF
Bit 6
—
(4)
(5)
reserved
Bit 5
RP0
GP5
T0IE
—
—
Write Buffer for the upper 5 bits of the Program Counter
CHS1
INTE
Bit 4
GP4
TO
—
CHS0
GPIE
Bit 3
GP3
PD
—
GO/DONE
Bit 2
GP2
T0IF
—
Z
reserved
INTF
Bit 1
GP1
DC
—
PIC12C67X
ADON
GPIF
Bit 0
GP0
—
C
0000 0000
xxxx xxxx
0000 0000
0001 1xxx
xxxx xxxx
11xx xxxx
---0 0000
0000 000x
-0-- ----
xxxx xxxx
0000 0000
Power-on
DS30561B-page 13
Value on
Reset
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
-0-- ----
uuuu uuuu
0000 0000
0000 0000
uuuu uuuu
0000 0000
000q quuu
uuuu uuuu
11uu uuuu
---0 0000
0000 000u
Resets
Value on
all other
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
—
(3)