ATMEGA16U2-AU Atmel, ATMEGA16U2-AU Datasheet - Page 207
ATMEGA16U2-AU
Manufacturer Part Number
ATMEGA16U2-AU
Description
MCU AVR 16K FLASH USB 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA16U2-AU
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
SPI, UART/USART, USB
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
22
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
SPI, UART
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
22
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT, AT90USBKEY, ATEVK525
Minimum Operating Temperature
- 40 C
For Use With
ATSTK600 - DEV KIT FOR AVR/AVR32ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Data Converters
-
Lead Free Status / Rohs Status
Details
Available stocks
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Part Number
Manufacturer
Quantity
Price
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21.15 Isochronous mode
21.15.1
21.15.2
21.16 Overflow
7799D–AVR–11/10
Underflow
CRC Error
The KILLBK bit is used to kill the last “written” bank. The best way to manage this abort is to per-
form the following operations:
Table 21-1.
An underflow can occur during IN stage if the host attempts to read a bank which is empty. In
this situation, the UNDERFI interrupt is triggered.
An underflow can also occur during OUT stage if the host send a packet while the banks are
already full. Typically, he CPU is not fast enough. The packet is lost.
It is not possible to have underflow error during OUT stage, in the CPU side, since the CPU
should read only if the bank is ready to give data (RXOUTI=1 or RWAL=1)
A CRC error can occur during OUT stage if the USB controller detects a bad received packet. In
this situation, the STALLEDI interrupt is triggered. This does not prevent the RXOUTI interrupt
from being triggered.
In Control, Isochronous, Bulk or Interrupt Endpoint, an overflow can occur during OUT stage, if
the host attempts to write in a bank that is too small for the packet. In this situation, the OVERFI
interrupt is triggered (if enabled). The packet is acknowledged and the RXOUTI interrupt is also
triggered (if enabled). The bank is filled with the first bytes of the packet.
• In a control transaction: ZLP data OUT received during a IN stage,
• In an isochronous IN transaction: ZLP data OUT received on the OUT endpoint during a IN
stage on the IN endpoint
Abort flow
NBUSYBK
Abort done
Endpoint
UEIENX.
Endpoint
TXINE
Abort
Clear
reset
=0
Yes
No
Yes
KILLBK=1
KILLBK=1
No
ATmega8U2/16U2/32U2
Disable the TXINI interrupt.
Abort is based on the fact
that no banks are busy,
meaning that nothing has to
be sent.
Kill the last written
bank.
Wait for the end of the
procedure.
207
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