ATTINY88-15MZ Atmel, ATTINY88-15MZ Datasheet - Page 135

• Manufacturer Part Number: ATTINY88-15MZ
• Description: IC MCU AVR 8B 8KB FLASH 32QFN
• Manufacturer: Atmel
• Series: AVR® ATtinyr

Specifications of ATTINY88-15MZ

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 16MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, WDT
• Number Of I /o: 28
• Program Memory Size: 8KB (4K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 64 x 8
• Ram Size: 512 x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

15.5.3
9157B–AVR–01/10
Bus Interface Unit
The TWI can be set to operate in high-speed mode, as described in
Register” on page
mode it relies on a prescaled version of the same. Depending on the clock signal used, the SCL
frequency is generated according to one of the following equations.
In normal mode:
In high-speed mode:
...where:
Note:
This unit contains the Data and Address Shift Register (TWDR), a START/STOP Controller and
Arbitration detection hardware. The TWDR contains the address or data bytes to be transmitted,
or the address or data bytes received. In addition to the 8-bit TWDR, the Bus Interface Unit also
contains a register containing the (N)ACK bit to be transmitted or received. This (N)ACK Regis-
ter is not directly accessible by the application software. However, when receiving, it can be set
or cleared by manipulating the TWI Control Register (TWCR). When in Transmitter mode, the
value of the received (N)ACK bit can be determined by the value in the TWSR.
The START/STOP Controller is responsible for generation and detection of START, REPEATED
START, and STOP conditions. The START/STOP controller is able to detect START and STOP
conditions even when the AVR MCU is in one of the sleep modes, enabling the MCU to wake up
if addressed by a Master.
If the TWI has initiated a transmission as Master, the Arbitration Detection hardware continu-
ously monitors the transmission trying to determine if arbitration is in process. If the TWI has lost
an arbitration, the Control Unit is informed. Correct action can then be taken and appropriate
status codes generated.
• clk
• clk
• TWBR = value of TWI Bit Rate Register, see
• TWPS = value of TWI prescaler, see
I/O
TWIHS
In TWI Master mode TWBR must be 10, or higher .
= prescaled system clock, see
= system clock, see
159. In high-speed mode the TWI uses the system clock, whereas in normal
f
f
SCL
SCL
Figure 6-1 on page 26
=
=
----------------------------------------------------------------------
16
----------------------------------------------------------------------
16
Figure 6-1 on page 26
Table 15-7 on page 157
+
+
2
2
clk
TWBR
TWBR
“TWBR – TWI Bit Rate Register” on page 155
clk
TWIHS
I/O
ATtiny88 Automotive
TWPS
TWPS
“TWHSR – TWI High Speed
135