ATtiny88 Atmel Corporation, ATtiny88 Datasheet
ATtiny88
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ATtiny88 Summary of contents
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Features • High Performance, Low Power AVR • Advanced RISC Architecture – 123 Powerful Instructions – Most Single Clock Cycle Execution – General Purpose Working Registers – Fully Static Operation • High Endurance Non-volatile Memory Segments – ...
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Pin Configurations Figure 1-1. Pinout of ATtiny48/88 (PCINT19/INT1) PD3 (PCINT20/T0) PD4 (PCINT26) PA2 VCC GND (PCINT27) PA3 (PCINT6/CLKI) PB6 (PCINT7) PB7 (PCINT19/INT1) PD3 (PCINT20/T0) PD4 VCC GND (PCINT6/CLKI) PB6 (PCINT7) PB7 (PCINT21/T1) PD5 NOTE: Bottom pad should be soldered ...
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Pin Descriptions 1.1.1 VCC Digital supply voltage. 1.1.2 AVCC AV is the supply voltage pin for the A/D converter and a selection of I/O pins. This pin should CC be externally connected to V mended this pin is connected ...
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The various special features of Port C are elaborated in 72. 1.1.8 Port D (PD7:0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). ...
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Overview The ATtiny48/ low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By executing powerful instructions in a single clock cycle, the ATtiny48/88 achieves throughputs approaching 1 MIPS per MHz allowing the system designer to ...
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... The ATtiny48/88 AVR is supported by a full suite of program and system development tools including: C compilers, macro assemblers, program debugger/simulators and evaluation kits. 2.2 Comparison Between ATtiny48 and ATtiny88 The ATtiny48 and ATtiny88 differ only in memory sizes, as summarised in Table 2-1. Device ATtiny48 ATtiny88 ...
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General Information 3.1 Resources A comprehensive set of development tools, application notes and datasheets are available for download at http://www.atmel.com/avr. 3.2 About Code Examples This documentation contains simple code examples that briefly show how to use various parts of ...
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AVR CPU Core 4.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...
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The fast-access Register File contains 32 x 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...
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Instruction Set Reference. This will in many cases remove the need for using the dedicated compare instructions, resulting in faster and more compact code. The Status Register is not automatically stored when entering an interrupt routine and ...
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As shown in directly into the first 32 locations of the user Data Space. Although not being physically imple- mented as SRAM locations, this memory organization provides great flexibility in access of the registers, as the X-, Y- and Z-pointer ...
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AVR devices all data memory can be addressed using SPL, only. In this case, the SPH register is not implemented. The stack pointer must be set to point above the I/O register areas, the minimum value being the lowest address ...
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This feature improves software security. See the section Device Signature” on page 188 The lowest addresses in the program memory space are by default defined as the Reset and Interrupt Vectors. The complete list of vectors is shown in ...
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CLI instruction. The following example shows how this can be used to avoid interrupts during the timed EEPROM write sequence. Assembly Code Example in r16, SREG cli sbi EECR, EEMPE sbi EECR, EEPE out SREG, r16 C Code Example char ...
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Register Description 4.9.1 SPH and SPL — Stack Pointer Registers Initial Value Read/Write Bit 0x3E (0x5E) 0x3D (0x5D) Bit Read/Write Initial Value • Bits 9:0 – SP[10:0]: Stack Pointer The Stack Pointer register points to the top of the ...
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Bit 3 – V: Two’s Complement Overflow Flag The Two’s Complement Overflow Flag V supports two’s complement arithmetics. See the “Instruction Set Description” for detailed information. • Bit 2 – N: Negative Flag The Negative Flag N indicates a ...
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... The Program Counter (PC) is 11/12 bits wide, thus capable of addressing all 4096/8192 loca- tions of program memory, as illustrated in Table 5-1. Device ATtiny48 ATtiny88 Constant tables can be allocated within the entire address space of program memory. See instructions LPM (Load Program Memory), and SPM (Store Program Memory) in Summary” on page device, as described in Timing diagrams for instruction fetch and execution are presented in ing” ...
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... Table 5-2. Device ATtiny48 ATtiny88 Note: The 512/768 memory locations include the general purpose register file, I/O register file, extended I/O register file, and the internal data memory. For compatibility with future devices, reserved bits should be written to zero, if accessed. ...
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ATtiny48/88 also contains three general purpose I/O registers that can be used for storing any information. See GPIOR0, GPIOR1 and GPIOR2 in general purpose I/O registers are particularly useful for storing global variables and status flags, since they are accessible ...
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Figure 5-2. 5.3 Data Memory (EEPROM) ATtiny48/88 contains 64 bytes of non-volatile data memory. This EEPROM is organized as a separate data space, in which single bytes can be read and written. All access registers are located in the I/O ...
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This can be done at times when the system allows time-critical operations, typically at start-up and initialisation. The programming method is selected using the EEPROM Programming Mode bits (EEPM1 and EEPM0) in EEPROM Control Register (EECR). ...
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To write an EEPROM memory location follow the procedure below: • Poll the EEPROM Program Enable bit (EEPE) in EEPROM Control Register (EECR) to make sure no other EEPROM operations are in process. If set, wait to clear. • Set ...
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Program Examples The following code examples show one assembly and one C function for erase, write, or atomic write of the EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts globally) so that no interrupts occur ...
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The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: ; Wait for completion ...
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Register Description 5.4.1 EEARH and EEARL – EEPROM Address Register Bit 0x21 (0x41) Read/Write Initial Value • Bits 15:6 – Res: Reserved Bits These bits are reserved and will always read zero. • Bits 5:0 – EEAR[5:0]: EEPROM Address ...
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Erase and Write can be split in two different operations. The programming times for the different modes are shown in Table 5-4. EEPM1 When EEPE is set any ...
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EEPROM access to fail recommended to have the Global Interrupt Flag cleared during all the steps to avoid these problems. When the write access time has elapsed, the EEPE bit is cleared by hardware. The user soft- ...
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Clock System Figure 6-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using different sleep modes, as described in ment and Sleep ...
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Flash Clock – clk FLASH The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul- taneously with the CPU clock. 6.1.4 Analog to Digital Converter Clock – clk The ADC is provided with ...
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Figure 6-2. When this clock source is selected, start-up times are determined by the SUT Fuses as shown in Table 6-2. Table 6-2. SUT[1: When applying an external clock required to avoid sudden changes ...
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When this oscillator is used as the chip clock, the Watchdog oscillator will still be used for the Watchdog Timer and for the Reset Time-out. For more information on the pre-programmed cali- bration value, see the section When this oscillator ...
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This can be used with all clock source options, and it will affect the clock frequency of the CPU and all synchronous peripherals. clk as shown in 6.3.1 Switching Prescaler Setting When switching between prescaler settings, the System ...
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Table 6-5. CKSEL[1:0] The main purpose of the delay is to keep the AVR in reset until it is supplied with minimum V The delay will not monitor the actual voltage and ...
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Register Description 6.6.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value The Oscillator Calibration Register is used to trim the internal oscillator to remove process varia- tions from the oscillator frequency. A pre-programmed calibration value is automatically ...
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The device is shipped with the CKDIV8 Fuse programmed. Table 6-6. CLKPS3 8008H–AVR–04/11 Clock Prescaler Select CLKPS2 CLKPS1 0 0 ...
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Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving power. The AVR provides various sleep modes allowing the user to tailor the power consump- tion to the application’s ...
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Idle mode enables the MCU to wake up from external triggered interrupts as well as internal ones like the SPI interrupts. If wake-up from the Analog Comparator interrupt is not required, the Analog Comparator can be powered down by setting ...
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Power-down mode, while a zero in this bit keeps BOD active. The default setting is zero, i.e. BOD active. Writing to the BODS bit is controlled by a timed sequence and an enable bit, see MCU Control Register” on page ...
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Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk ...
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MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bits 7, 3:0 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 6 – BODS: BOD Sleep The BODS bit must ...
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Bit 3 – PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • Bit 2 – PRSPI: Power Reduction Serial ...
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System Control and Reset 8.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be an RJMP ...
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Reset Sources The ATtiny48/88 has four sources of reset: • Power-on Reset. The MCU is reset when the supply voltage is below the Power-on Reset threshold (V • External Reset. The MCU is reset when a low level is ...
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External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see running. Shorter pulses are not guaranteed to generate a reset. When the applied signal reaches ...
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Watchdog Reset When the Watchdog times out, it will generate a short reset pulse of one CK cycle duration. On the falling edge of this pulse, the delay timer starts counting the Time-out period t page 46 Figure 8-6. ...
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Watchdog Timer ATtiny48/88 has an Enhanced Watchdog Timer (WDT). The WDT is a timer counting cycles of a separate on-chip 128 kHz oscillator. The WDT gives an interrupt or a system reset when the counter reaches a given time-out ...
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The following code example shows one assembly and one C function for turning off the Watch- dog Timer. The example assumes that interrupts are controlled (e.g. by disabling interrupts globally) so that no interrupts will occur during the execution of ...
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Watchdog System Reset Flag (WDRF) and the WDE control bit in the initialization routine, even if the Watchdog is not in use. The following code example shows one assembly and one C ...
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Register Description 8.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x34 (0x54) Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved ...
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Watchdog Timer security while using the interrupt. To stay in Interrupt and System Reset Mode, WDIE must be set after each interrupt. This should however not be done within the interrupt service routine itself, as this ...
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Table 8-2. WDP3 Notes: 8008H–AVR–04/11 Watchdog Timer Prescale Select (Continued) WDP2 WDP1 WDP0 selected, ...
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Interrupts This section describes the specifics of interrupt handling in ATtiny48/88. For a general explana- tion of the AVR interrupt handling, refer to 9.1 Interrupt Vectors Table 9-1. Vector No ...
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A typical and general setup for interrupt vector addresses in ATtiny48/88 is shown in the pro- gram example below. Assembly Code Example .org 0x0000 RESET: Note: 9.2 External Interrupts The External Interrupts are triggered by the INT0 and INT1 pins ...
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Idle mode. The INT0 and INT1 interrupts can be triggered by a falling or rising edge low level. This is configured ...
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The start-up time is defined by the SUT and CKSEL Fuses as described in Table 6-5 on page If the low level on the interrupt pin is removed before the device has woken up then program ...
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Table 9-3. ISC01 9.3.2 EIMSK – External Interrupt Mask Register Bit 0x1D (0x3D) Read/Write Initial Value • ...
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Interrupt Vector. The flag is cleared when the interrupt routine is executed. Alternatively, the flag can be cleared by writing a logical one to it. This flag is always cleared when INT1 is configured as a level interrupt. • ...
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PCIFR – Pin Change Interrupt Flag Register Bit 0x1B (0x3B) Read/Write Initial Value • Bits 7:4 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 3 – PCIF3: Pin Change Interrupt Flag 3 ...
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PCMSK2 – Pin Change Mask Register 2 Bit (0x6D) Read/Write Initial Value • Bits 7:0 – PCINT[23:16]: Pin Change Enable Mask 23:16 Each PCINT[23:16] bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT[23:16] ...
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I/O-Ports 10.1 Introduction All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...
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Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 10-2. General Digital I/O Pxn Note: 10.2.1 Configuring the Pin Each port pin ...
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If PORTxn is written logic one when the pin is configured as an output pin, the port pin is driven high (one). If PORTxn is written logic zero when the pin is configured as an output pin, the port pin ...
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Table 10-1 Table 10-1. DDxn Note: 10.2.5 Reading the Pin Value Independent of the setting of Data Direction bit DDxn, the port pin can be read through the PINxn Register bit. As shown in stitute ...
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Figure 10-5. Synchronization when Reading a Software Assigned Pin Value INSTRUCTIONS The following code example shows how to set port B pins 0 and 1 high, 2 and 3 low, and define the port pins from ...
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C Code Example unsigned char i; 10.2.6 Digital Input Enable and Sleep Modes As shown in Schmitt Trigger. The signal denoted SLEEP in the figure, is set by the MCU Sleep Controller in Power-down mode to avoid high power consumption ...
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Figure 10-6. Alternate Port Functions Pxn PUOExn: PUOVxn: DDOExn: DDOVxn: PVOExn: PVOVxn: DIEOExn: Pxn DIGITAL INPUT-ENABLE OVERRIDE ENABLE DIEOVxn: Pxn DIGITAL INPUT-ENABLE OVERRIDE VALUE SLEEP: PTOExn: Note: ATtiny48/88 66 (1) PUOExn PUOVxn 1 0 DDOExn DDOVxn 1 0 PVOExn PVOVxn ...
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Table 10-2 ure 10-6 in the modules having the alternate function. Table 10-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the ...
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Alternate Functions of Port A The Port A pins with alternate functions are shown in Table 10-3. Port Pin The alternate pin configuration is as follows: • PCINT27 – Port A, Bit 3 PCINT27: Pin Change Interrupt source 27. ...
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Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 10-5. Port Pin PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 The alternate pin configuration is as follows: • PCINT7 – Port B, ...
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PCINT4: Pin Change Interrupt source 4. The PB4 pin can serve as an external interrupt source. • MOSI/PCINT3 – Port B, Bit 3 MOSI: SPI Master Data output, Slave Data input for SPI channel. When the SPI is enabled as ...
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Table 10-6. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Notes: Table 10-7. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 8008H–AVR–04/11 Overriding Signals for Alternate Functions in PB[7:4] PB7/ PB6/CLKI/ (1) ...
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Alternate Functions of Port C The Port C pins with alternate functions are shown in Table 10-8. Port Pin PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 The alternate pin configuration is as follows: • PCINT15 – Port C, ...
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PCINT13: Pin Change Interrupt source 13. The PC5 pin can serve as an external interrupt source. • SDA/ADC4/PCINT12 – Port C, Bit 4 SDA, 2-wire Serial Interface Data: When the TWEN bit in TWCR is set (one) to enable the ...
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Table 10-9 shown in Table 10-9. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO Note: Table 10-10. Overriding Signals for Alternate Functions in PC[3:0] Signal Name PUOE PUOV DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO ...
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Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 10-11. Port D Pins Alternate Functions Port Pin The alternate pin configuration is as follows: • AIN1/PCINT23 – Port D, Bit 7 AIN1: ...
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INT1/PCINT19 – Port D, Bit 3 INT1, External Interrupt source 1: The PD3 pin can serve as an external interrupt source. PCINT19: Pin Change Interrupt source 19. The PD3 pin can serve as an external interrupt source. • INT0/PCINT18 ...
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Table 10-13. Overriding Signals for Alternate Functions in PD[3:0] Signal Name PUOE PUO DDOE DDOV PVOE PVOV DIEOE DIEOV DI AIO 10.4 Register Description 10.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – ...
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MCUCR register. See feature. 10.4.3 PORTA – The Port A Data Register Bit 0x0E (0x2E) Read/Write Initial Value 10.4.4 DDRA – The Port A Data Direction Register Bit 0x0D (0x2D) Read/Write Initial Value 10.4.5 PINA – The Port ...
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PINC – The Port C Input Pins Bit 0x06 (0x26) Read/Write Initial Value 10.4.12 PORTD – The Port D Data Register Bit 0x0B (0x2B) Read/Write Initial Value 10.4.13 DDRD – The Port D Data Direction Register Bit 0x0A (0x2A) ...
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Timer/Counter0 11.1 Features • Two Independent Output Compare Units • Clear Timer on Compare Match (Auto Reload) • Three Independent Interrupt Sources (TOV0, OCF0A, and OCF0B) 11.2 Overview Timer/Counter0 is a general purpose 8-bit Timer/Counter module, with two ...
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TCNT0 for accessing Timer/Counter0 counter value and so on. The definitions in Table 11-1. MAX TOP 11.2.2 Registers The Timer/Counter (TCNT0) and Output Compare Registers (OCR0A ...
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Signal description (internal signals): count clear clk top Depending of the mode of operation used, the counter is cleared or incremented at each timer clock (clk Clock Select bits (CS0[2:0]). When no clock source is selected (CS0[2: the ...
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TCNT0 without triggering an interrupt when the Timer/Counter clock is enabled. 11.5.2 Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock ...
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An interrupt can be generated each time the counter value reaches the TOP value by using the OCF0A Flag. If the interrupt is enabled, the interrupt handler routine can be used for updating the TOP value. However, changing TOP to ...
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Figure 11-7. Timer/Counter Timing Diagram, Setting of OCF0x, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 11-8 is TOP. Figure 11-8. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- clk clk (clk TCNTn (CTC) OCRnx ...
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Table 11-2. Mode 0 1 Notes: • Bits 2:0 – CS0[2:0]: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter. Table 11-3. CS02 ...
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OCR0B – Output Compare Register B Bit 0x28 (0x48) Read/Write Initial Value The Output Compare Register B contains an 8-bit value that is continuously compared with the counter value (TCNT0). A match can be used to generate an Output ...
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Bit 1 – OCF0A: Timer/Counter 0 Output Compare A Match Flag The OCF0A bit is set when a Compare Match occurs between the Timer/Counter0 and the data in OCR0A – Output Compare Register0. OCF0A is cleared by hardware when ...
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Timer/Counter1 with PWM 12.1 Features • True 16-bit Design (i.e., Allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer ...
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For actual placement of I/O pins, refer to Registers, including I/O bits and I/O pins, are shown in bold. The device-specific I/O Register and bit locations are listed in the The PRTIM1 bit in enable Timer/Counter1 module. 12.2.1 Registers The ...
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Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit ...
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It is important to notice that accessing 16-bit registers are atomic operations interrupt occurs between the two instructions accessing the 16-bit register, and the interrupt code updates the temporary register by accessing the same or any other of ...
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The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...
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Timer/Counter Control Register B (TCCR1B). For details on clock sources and prescaler, see 12.5 Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 12-2 Figure 12-2. Counter Unit Block ...
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Output Compare outputs OC1x. For more details about advanced counting sequences and waveform generation, see The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM1[3:0] bits. TOV1 can be ...
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Reading the 16-bit value in the Input Capture Register (ICR1) is done by first reading the low byte (ICR1L) and then the high byte (ICR1H). When the low byte is read the high byte is copied into the high byte ...
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Using the Input Capture unit in any mode of operation when the TOP value (resolution) is actively changed during operation, is not recommended. Measurement of an external signal’s duty cycle requires that the trigger edge is changed after each capture. ...
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The OCR1x Register is double buffered when using any of the twelve Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. The double buffering synchronizes the update ...
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Compare Match Output Unit The Compare Output mode (COM1x[1:0]) bits have two functions. The Waveform Generator uses the COM1x[1:0] bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x[1:0] bits control the OC1x ...
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Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x[1:0] bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x[1: tells the Waveform Generator that no action on the OC1x Register ...
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The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 12-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can ...
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PWM mode can be twice as high as the phase correct and phase and frequency correct PWM modes that use dual-slope operation. This high fre- quency makes the fast PWM mode well suited ...
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The procedure for updating ICR1 differs from updating OCR1A when used for defining the TOP value. The ICR1 Register is not double buffered. This means that if ICR1 is changed to a low value when the counter is running with ...
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The dual-slope operation has lower maximum operation frequency than single slope operation. However, due to the symmetric feature of the dual-slope PWM modes, these modes are preferred for motor control applications. The PWM resolution for the phase correct PWM ...
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When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a ...
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The main difference between the phase correct, and the phase and frequency correct PWM mode is the time the OCR1x Register is updated by the OCR1x Buffer Register, (see 8 and Figure The PWM resolution for the phase and frequency ...
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When changing the TOP value the program must ensure that the new TOP value is higher or equal to the value of all of the Compare Registers. If the TOP value is lower than any of the Compare Registers, a ...
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Figure 12-10. Timer/Counter Timing Diagram, Setting of OCF1x, no Prescaling clk I/O clk Tn (clk /1) I/O TCNTn OCRnx OCFnx Figure 12-11 Figure 12-11. Timer/Counter Timing Diagram, Setting of OCF1x, with Prescaler (f clk I/O clk Tn (clk /8) I/O ...
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Figure 12-12. Timer/Counter Timing Diagram, no Prescaling clk clk (clk TCNTn (CTC and FPWM) TCNTn (PC and PFC PWM) TOVn and ICFn as TOP) OCRnx (Update at TOP) Figure 12-13 Figure 12-13. Timer/Counter Timing Diagram, with Prescaler (f (clk TCNTn ...
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Register Description 12.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bits 7:6 – COM1A[1:0]: Compare Output Mode for Channel A • Bits 5:4 – COM1B[1:0]: Compare Output Mode for Channel B The COM1A[1:0] and ...
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Table 12-4 correct or the phase and frequency correct, PWM mode. Table 12-4. COM1A1 COM1B1 Note: • Bits 3:2 – Res: Reserved Bits These bits are reserved and will always read zero. • Bits 1:0 – ...
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Modes of operation supported by the Timer/Counter unit are: Normal mode (counter), Clear Timer on Compare match (CTC) mode, and three types of Pulse Width Modulation (PWM) modes. 12.11.2 TCCR1B – Timer/Counter1 Control Register B Bit (0x81) Read/Write Initial Value ...
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Table 12-6. CS12 external pin modes are used for the Timer/Counter1, transitions on the T1 pin will clock the counter even if the pin is configured as an output. This feature allows software control of the ...
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Writing to the TCNT1 Register blocks (removes) the compare match on the following timer clock for all compare units. 12.11.5 OCR1AH and OCR1AL – Output Compare Register 1 A Bit (0x89) (0x88) Read/Write Initial Value 12.11.6 OCR1BH and OCR1BL – ...
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Bit 5 – ICIE1: Timer/Counter1, Input Capture Interrupt Enable When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally enabled), the Timer/Counter1 Input Capture interrupt is enabled. The corresponding Interrupt Vector ...
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OCF1B is automatically cleared when the Output Compare Match B Interrupt Vector is exe- cuted. Alternatively, OCF1B can be cleared by writing a logic one to its bit location. • Bit 1 – OCF1A: Timer/Counter1, Output Compare A Match Flag ...
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Timer/Counter0 and Timer/Counter1 Prescalers “8-bit Timer/Counter0” on page 80 same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 13.1 Internal Clock Source The Timer/Counter can be clocked directly ...
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Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the ...
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When the TSM bit is written to zero, the PSRSYNC bit are cleared by hardware, and the Timer/Counters start counting simultaneously. • Bits 6:1 – Res: Reserved Bits These bits are reserved and will always read zero. • Bit 0 ...
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SPI – Serial Peripheral Interface 14.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...
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The PRSPI bit in enable the SPI module. The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling ...
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When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to “Alternate Port Functions” on page Table 14-1. Pin MOSI MISO SCK SS Note: The following code examples show how to ...
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C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: Note: 8008H–AVR–04/11 ...
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C Code Example void SPI_SlaveInit(void Set MISO output, all others input */ DDR_SPI = (1<<DD_MISO); /* Enable SPI */ SPCR = (1<<SPE); } char SPI_SlaveReceive(void Wait for reception complete */ while(!(SPSR & (1<<SPIF))) /* Return Data ...
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Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi- bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the MSTR bit has been cleared ...
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Data bits are shifted out and latched in on opposite edges of the SCK signal, ensuring sufficient time for data signals to stabilize. This is clearly seen by summarizing and Table 14-4 on page Table 14-2. CPOL ...
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Bit 2 – CPHA: Clock Phase The settings of the Clock Phase bit (CPHA) determine if data is sampled on the leading (first) or trailing (last) edge of SCK. Refer to functionality is summarized below: Table 14-4. • Bits ...
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Bit 0 – SPI2X: Double SPI Speed Bit When this bit is written logic one the SPI speed (SCK Frequency) will be doubled when the SPI is in Master mode (see clock periods. When the SPI is configured as ...
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TWI – Two Wire Interface 15.1 Features • Phillips I • SMBus compatible (with reservations) • Simple Yet Powerful and Flexible Communication Interface, only two Bus Lines Needed • Both Master and Slave Operation Supported • Device can Operate ...
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TWI Terminology The following definitions are frequently encountered in this section. Table 15-1. Term Master Slave Transmitter Receiver The PRTWI bit in enable the 2-wire Serial Interface. 15.3.2 Electrical Interconnection As depicted in pull-up resistors. The bus drivers of ...
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START and STOP Conditions The Master initiates and terminates a data transmission. The transmission is initiated when the Master issues a START condition on the bus, and it is terminated when the Master issues a STOP condition. Between a ...
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The MSB of the address byte is transmitted first. Slave addresses can freely be allocated by the designer, but the address 0000 000 is reserved for a general call. When a general call is issued, all slaves should respond by ...
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Figure 15-6. Typical Data Transmission SDA SCL START 15.5 Multi-master Bus Systems, Arbitration and Synchronization The TWI protocol allows bus systems with several masters. Special concerns have been taken in order to ensure that transmissions will proceed as normal, even ...
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The wired-ANDing of the bus lines is used to solve both these problems. The serial clocks from all masters will be wired-ANDed, yielding a combined clock with a high period equal to the one from the Master with the shortest ...
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Overview of the TWI Module The TWI module is comprised of several submodules, as shown in drawn in a thick line are accessible through the AVR data bus. Figure 15-9. Overview of the TWI Module 15.6.1 SCL and SDA ...
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The TWI can be set to operate in high-speed mode, as described in Register” on page mode it relies on a prescaled version of the same. Depending on the clock signal used, the SCL frequency is generated according to one ...
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MCU to wake up if addressed by a Master. If another interrupt (e.g., INT0) occurs during TWI Power-down address match and wakes up the CPU, the TWI aborts opera- tion and return to it’s idle state. If ...
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Figure 15-10. Interfacing the Application to the TWI in a Typical Transmission 3. Check TWSR to see if START was 1. Application sent. Application loads SLA+W into writes to TWCR to TWDR, and loads appropriate control initiate signals into TWCR, ...
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TWINT bit is set in the value written. Writing a one to TWINT clears the flag. The TWI will not start any operation as long as the TWINT bit in TWCR is set. Immedi- ately after the application ...
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Assembly Code Example in r16,TWSR andi r16, 0xF8 cpi r16, START brne ERROR 3 r16, SLA_W ldi out TWDR, r16 ldi r16, (1<<TWINT) | (1<<TWEN) out TWCR, r16 wait2: in r16,TWCR 4 sbrs r16,TWINT rjmp wait2 in r16,TWSR andi r16, ...
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The following sections describe each of these modes. Possible status codes are described along with figures detailing data transmission in each of the modes. These figures contain the following abbreviations: S: START condition Rs: REPEATED START condition R: Read bit ...
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A START condition is sent by writing the following value to TWCR: TWCR value TWEN must be set to enable the 2-wire Serial Interface, TWSTA must be written to one to trans- mit a START condition and TWINT must be ...
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Master to switch between Slaves, Master Transmitter mode and Master Receiver mode with- out losing control of the bus. Table 15-2. Status codes for Master Transmitter Mode Status Code (TWSR) Status of the 2-wire Serial Bus Prescaler Bits and ...
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Figure 15-12. Formats and States in the Master Transmitter Mode Successfull transmission to a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Not acknowledge received after a data byte Arbitration lost ...
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Figure 15-13. Data Transfer in Master Receiver Mode SDA SCL A START condition is sent by writing the following value to TWCR: TWCR value TWEN must be written to one to enable the 2-wire Serial Interface, TWSTA must be written ...
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After a repeated START condition (state 0x10) the 2-wire Serial Interface can access the same Slave again new Slave without transmitting a STOP condition. Repeated START enables the Master to switch between Slaves, Master Transmitter mode and Master ...
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Figure 15-14. Formats and States in the Master Receiver Mode Successfull reception from a slave receiver Next transfer started with a repeated start condition Not acknowledge received after the slave address Arbitration lost in slave address or data byte Arbitration ...
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To initiate the Slave Receiver mode, TWAR and TWCR must be initialized as follows: TWAR value The upper 7 bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is ...
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Table 15-4. Status Codes for Slave Receiver Mode Status Code (TWSR) Status of the 2-wire Serial Bus Prescaler Bits and 2-wire Serial Interface Hard- are 0 ware 0x60 Own SLA+W has been received; ACK has been returned 0x68 Arbitration lost ...
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Figure 15-16. Formats and States in the Slave Receiver Mode Reception of the own slave address and one or more data bytes. All are acknowledged Last data byte received is not acknowledged Arbitration lost as master and addressed as slave ...
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To initiate the Slave Transmitter mode, TWAR and TWCR must be initialized as follows: TWAR value The upper seven bits are the address to which the 2-wire Serial Interface will respond when addressed by a Master. If the LSB is ...
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Table 15-5. Status Codes for Slave Transmitter Mode Status Code (TWSR) Status of the 2-wire Serial Bus Prescaler and 2-wire Serial Interface Hard- Bits ware are 0 0xA8 Own SLA+R has been received; ACK has been returned 0xB0 Arbitration lost ...
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Figure 15-18. Formats and States in the Slave Transmitter Mode Reception of the own slave address and one or more data bytes Arbitration lost as master and addressed as slave Last data byte transmitted. Switched to not addressed slave (TWEA ...
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Combining Several TWI Modes In some cases, several TWI modes must be combined in order to complete the desired action. Consider for example reading data from a serial EEPROM. Typically, such a transfer involves the following steps: 1. The ...
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Figure 15-20. An Arbitration Example Several different scenarios may arise during arbitration, as described below: • Two or more masters are performing identical communication with the same Slave. In this case, neither the Slave nor any of the masters will ...
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Compatibility with SMBus As with any other I should be aware of before connecting a TWI device to SMBus devices. For use in SMBus envi- ronments, the following should be noted: • All I/O pins of an AVR, including ...
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TWI, so all accesses to the TWI Address Register (TWAR), TWI Sta- tus Register (TWSR), and TWI Data Register (TWDR) must be complete before clearing this flag. • Bit 6 – TWEA: TWI Enable Acknowledge ...
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Bit 5 – TWSTA: TWI START Condition Bit The application writes the TWSTA bit to one when it desires to become a Master on the 2-wire Serial Bus. The TWI hardware checks if the bus is available, and generates ...
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Bits 1:0 – TWPS: TWI Prescaler Bits These bits can be read and written, and control the bit rate prescaler. Table 15-7. TWPS1 calculate bit rates, see in the equation. 15.11.4 TWDR – TWI ...
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Bit 0 – TWGCE: TWI General Call Recognition Enable Bit If set, this bit enables the recognition of a General Call given over the 2-wire Serial Bus. 15.11.6 TWAMR – TWI (Slave) Address Mask Register Bit (0xBD) Read/Write Initial ...
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Analog Comparator The Analog Comparator compares the input values on the positive pin AIN0 and negative pin AIN1. When the voltage on the positive pin AIN0 is higher than the voltage on the negative pin AIN1, the Analog Comparator ...
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Table 16-1. ACME 16.2 Register Description 16.2.1 ADCSRB – ADC Control and Status Register B Bit (0x7B) Read/Write Initial Value • Bit 6 – ACME: Analog Comparator Multiplexer Enable When this bit is written ...
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Bit 4 – ACI: Analog Comparator Interrupt Flag This bit is set by hardware when a comparator output event triggers the interrupt mode defined by ACIS1 and ACIS0. The Analog Comparator interrupt routine is executed if the ACIE bit ...
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ADC – Analog to Digital Converter 17.1 Features • 10-bit Resolution • 1 LSB Integral Non-linearity • ± 2 LSB Absolute Accuracy • 14 µs Conversion Time • 15 kSPS at Maximum Resolution • Six Multiplexed Single Ended Input ...
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Figure 17-1. Analog to Digital Converter Block Schematic Operation AVCC INTERNAL 1.1V GND REFERENCE TEMPERATURE ADC7 ADC6 ADC5 ADC4 ADC3 ADC2 ADC1 ADC0 17.3 Operation In order to be able to use the ADC the Power Reduction bit, PRADC, in ...
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The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended inputs to the ADC. ...
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Figure 17-2. ADC Auto Trigger Logic Using the ADC Interrupt Flag as a trigger source makes the ADC start a new conversion as soon as the ongoing conversion has finished. The ADC then operates in Free Running mode, con- stantly ...
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The ADC module contains a prescaler, as illustrated in ates an acceptable ADC clock frequency from any CPU frequency above 100 kHz. The prescaling is set by the ADPS bits in ADCSRA. The prescaler starts counting from the moment the ...
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When Auto Triggering is used, the prescaler is reset when the trigger event occurs, as shown in Figure mode, the sample-and-hold takes place two ADC clock cycles after the rising edge on the trigger source signal. Three additional CPU clock ...
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For a summary of conversion times, see Table 17-1. Condition First conversion Normal conversions, single ended Auto Triggered conversions Free Running conversions 17.6 Changing Channel or Reference Selection Bits MUXn and REFS0 in the ADMUX Register are single buffered through ...
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Since the next conversion has already started automatically, the next result will reflect the previous channel selection. Subsequent conversions will reflect the new channel selection. 17.6.2 ADC Voltage Reference The ADC reference voltage (V channels that exceed V AV ...
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Figure 17-8. Analog Input Circuitry Note: 17.9 Analog Noise Canceling Techniques Digital circuitry inside and outside the device generates EMI which might affect the accuracy of analog measurements. When conversion accuracy is critical, the noise level can be reduced by ...
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Where high ADC accuracy is required it is recommended to use ADC Noise Reduction Mode, as described in is above 1 MHz, or when the ADC is used for reading the internal temperature sensor, as described in bypass capacitors does ...
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Gain error: After adjusting for offset, the gain error is found as the deviation of the last transition (0x3FE to 0x3FF) compared to the ideal transition (at 1.5 LSB below maximum). Ideal value: 0 LSB Figure 17-11. Gain Error ...
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Differential Non-linearity (DNL): The maximum deviation of the actual code width (the interval between two adjacent transitions) from the ideal code width (1 LSB). Ideal value: 0 LSB. Figure 17-13. Differential Non-linearity (DNL) • Quantization Error: Due to the ...
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ADMUX register to “1000” enables the temperature sensor. The internal 1.1V voltage reference must also be selected for the ADC voltage reference source in the temperature sensor measure- ment. When the temperature sensor is enabled, the ADC converter can be ...
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Bit 5 – ADLAR: ADC Left Adjust Result The ADLAR bit affects the presentation of the ADC conversion result in the ADC Data Register. Write one to ADLAR to left adjust the result. Otherwise, the result is right adjusted. ...
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ADCSRA – ADC Control and Status Register A Bit (0x7A) Read/Write Initial Value • Bit 7 – ADEN: ADC Enable Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning ...
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Table 17-5. ADPS2 17.13.3 ADCL and ADCH – The ADC Data Register 17.13.3.1 ADLAR = 0 Bit (0x79) (0x78) Read/Write Initial Value 17.13.3.2 ADLAR = 1 Bit (0x79) (0x78) Read/Write Initial Value • ADC[9:0]: ADC Conversion Result ...
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Bits 2:0 – ADTS[2:0]: ADC Auto Trigger Source If ADATE in ADCSRA is written to one, the value of these bits selects which source will trigger an ADC conversion. If ADATE is cleared, the ADTS[2:0] settings will have no ...
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On-Chip Debug System 18.1 Features • Complete Program Flow Control • Emulates All On-Chip Functions, Both Digital and Analog, except RESET Pin • Real-time Operation • Symbolic Debugging Support (Both at C and Assembler Source Level, or for ...
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When designing a system where debugWIRE will be used, the following observations must be made for correct operation: • Pull-up resistors on the dW/(RESET) line must not be smaller than 10kΩ. The pull-up resistor is not required for debugWIRE functionality. ...
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Self-Programming the Flash The device provides a Self-Programming mechanism for downloading and uploading program code by the MCU itself. The Self-Programming can use any available data interface and associ- ated protocol to read code and write (program) that code ...
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Performing a Page Write To execute Page Write, set up the address in the Z-pointer, write “00000101” to SPMCSR and execute SPM within four clock cycles after writing SPMCSR. The data in R1 and R0 is ignored. The page ...
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EEPROM Write Prevents Writing to SPMCSR Note that an EEPROM write operation will block all software programming to Flash. Reading the Fuses and Lock bits from software will also be prevented during the EEPROM write operation recommended ...
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Preventing Flash Corruption During periods of low V too low for the CPU and the Flash to operate properly. These issues are the same as for board level systems using the Flash, and the same design solutions should be ...
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Bit 5 – Res: Reserved Bit This bit is reserved and will always read zero. • Bit 4 – CTPB: Clear Temporary Page Buffer If the CTPB bit is written while filling the temporary page buffer, the temporary page ...
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Lock Bits, Fuse Bits and Device Signature 20.1 Lock Bits ATtiny48/88 provide the program and data memory lock bits listed in Table 20-1. Lock Bit Byte LB2 LB1 Notes: Lock bits can be left unprogrammed (“1”) or can be ...
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Fuse Bits The ATtiny48/88 has three Fuse bytes. of all the fuses and how they are mapped into the Fuse bytes. Note that the fuses are read as logical zero, “0”, if they are programmed. Table 20-3. Fuse Extended ...
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... Table 20-6. Table 20-6. Part ATtiny48 ATtiny88 20.4 Calibration Byte The ATtiny48/88 has a byte calibration value for the internal oscillator. This byte resides in the high byte of address 0x000 in the signature address space. During reset, this byte is automati- cally written into the OSCCAL Register to ensure correct frequency of the calibrated oscillator. ...
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... Memory Parametrics Flash memory parametrics are summarised in Table 21-1. Device ATtiny48 ATtiny88 EEPROM parametrics are summarised in Table 21-2. Device ATtiny48 ATtiny88 21.2 Parallel Programming Parallel programming signals and connections are illustrated in Figure 21-1. Parallel Programming Signals 8008H–AVR–04/11 Table Flash Parametrics Flash Size Page Size ...
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Signals are described in names. Table 21-3. Signal Name in Programming Mode RDY/BSY OE WR BS1 XA0 XA1 PAGEL BS2 DATA Note: Pulses are assumed least 250 ns, unless otherwise noted. Table 21-4. The XA1/XA0 pins determine ...
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When pulsing WR or OE, the command loaded determines the action executed. The different Commands are shown in Table 21-6. Command Byte 1000 0000 0100 0000 0010 0000 0001 0000 0001 0001 0000 1000 0000 0100 0000 0010 0000 0011 ...
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The command needs only be loaded once when writing or reading multiple memory locations. • Skip writing the data value 0xFF, that is the contents of the entire EEPROM (unless the EESAVE Fuse is programmed) and Flash after a ...
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Give CLKI a positive pulse. This loads the data byte. D. Load Data High Byte 1. Set BS1 to “1”. This selects high data byte. 2. Set XA1, XA0 to “01”. This enables data loading. 3. Set DATA = ...
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Flash page addressing is illustrated in 21-1 on page 191 Figure 21-2. Addressing the Flash Which is Organized in Pages PROGRAM MEMORY Flash programming waveforms are illustrated in letters refer to the programming steps described earlier. Figure 21-3. Programming the ...
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The programming algorithm for the EEPROM data memory is as follows (refer to Data loading): • A: Load command “0001 0001” • G: Load address high byte (0x00 – 0xFF) • B: Load address low byte (0x00 – ...
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Set BS1 to “1”. The Flash word high byte can now be read at DATA • Set OE to “1” 21.2.7 Reading the EEPROM The algorithm for reading the EEPROM memory is as follows (see page 194 • A: ...
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Figure 21-5. Programming the FUSES Waveforms DATA XA1 XA0 BS1 BS2 CLKI WR RDY/BSY RESET +12V OE PAGEL 21.2.11 Programming the Lock Bits The algorithm for programming the lock bits is as follows (see 194 for details on command and ...
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Figure 21-6. Mapping Between BS1, BS2 and the Fuse and Lock Bits During Read Fuse Low Byte Extended Fuse Byte Fuse High Byte 21.2.13 Reading Signature Bytes The algorithm for reading the signature bytes is as follows (see page 194 ...