PIC16LC716-04I/P Microchip Technology, PIC16LC716-04I/P Datasheet - Page 18
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PIC16LC716-04I/P
Manufacturer Part Number
PIC16LC716-04I/P
Description
IC MCU OTP 2KX14 A/D PWM 18DIP
Manufacturer
Microchip Technology
Series
PIC® 16Cr
Datasheet
1.PIC16C716-04P.pdf
(106 pages)
Specifications of PIC16LC716-04I/P
Core Processor
PIC
Core Size
8-Bit
Speed
4MHz
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
13
Program Memory Size
3.5KB (2K x 14)
Program Memory Type
OTP
Ram Size
128 x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 5.5 V
Data Converters
A/D 4x8b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
18-DIP (0.300", 7.62mm)
Processor Series
PIC16LC
Core
PIC
Data Bus Width
8 bit
Data Ram Size
128 B
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
13
Number Of Timers
3 bit
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
ICE2000
Minimum Operating Temperature
- 40 C
On-chip Adc
4 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Connectivity
-
Lead Free Status / Rohs Status
Details
PIC16C712/716
2.2.2.4
This register contains the individual enable bits for the
peripheral interrupts.
FIGURE 2-7:
DS41106B-page 16
bit7
bit 7:
bit 6:
bit 5-3: Unimplemented: Read as ‘0’
bit 2:
bit 1:
bit 0:
U-0
—
Unimplemented: Read as ‘0’
ADIE: A/D Converter Interrupt Enable bit
1 = Enables the A/D interrupt
0 = Disables the A/D interrupt
CCP1IE: CCP1 Interrupt Enable bit
1 = Enables the CCP1 interrupt
0 = Disables the CCP1 interrupt
TMR2IE: TMR2 to PR2 Match Interrupt Enable bit
1 = Enables the TMR2 to PR2 match interrupt
0 = Disables the TMR2 to PR2 match interrupt
TMR1IE: TMR1 Overflow Interrupt Enable bit
1 = Enables the TMR1 overflow interrupt
0 = Disables the TMR1 overflow interrupt
PIE1 Register
R/W-0
ADIE
PIE1 REGISTER (ADDRESS 8Ch)
U-0
—
U-0
—
R/W-0
—
CCP1IE
R/W-0
TMR2IE
R/W-0
Note:
TMR1IE
R/W-0
Bit PEIE (INTCON<6>) must be set to
enable any peripheral interrupt.
bit0
R = Readable bit
W = Writable bit
U = Unimplemented bit,
-n = Value at POR Reset
© 2005 Microchip Technology Inc.
read as ‘0’