ATMEGA328-AUR Atmel, ATMEGA328-AUR Datasheet - Page 91
![IC MCU AVR 32K FLASH 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA328-AUR
Manufacturer Part Number
ATMEGA328-AUR
Description
IC MCU AVR 32K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA328-AUR
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
1K x 8
Ram Size
2K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8271C–AVR–08/10
• INT0/PCINT18 – Port D, Bit 2
INT0, External Interrupt source 0: The PD2 pin can serve as an external interrupt source.
PCINT18: Pin Change Interrupt source 18. The PD2 pin can serve as an external interrupt
source.
• TXD/PCINT17 – Port D, Bit 1
TXD, Transmit Data (Data output pin for the USART). When the USART Transmitter is enabled,
this pin is configured as an output regardless of the value of DDD1.
PCINT17: Pin Change Interrupt source 17. The PD1 pin can serve as an external interrupt
source.
• RXD/PCINT16 – Port D, Bit 0
RXD, Receive Data (Data input pin for the USART). When the USART Receiver is enabled this
pin is configured as an input regardless of the value of DDD0. When the USART forces this pin
to be an input, the pull-up can still be controlled by the PORTD0 bit.
PCINT16: Pin Change Interrupt source 16. The PD0 pin can serve as an external interrupt
source.
Table 13-10
shown in
Table 13-10. Overriding Signals for Alternate Functions PD7...PD4
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
Signal
Name
PUOE
PUO
DDOE
DDOV
PVOE
PVOV
DIEOE
DIEOV
DI
AIO
Figure 13-5 on page
PD7/AIN1
/PCINT23
0
0
0
0
0
0
PCINT23 • PCIE2
1
PCINT23 INPUT
AIN1 INPUT
and
Table 13-11
81.
relate the alternate functions of Port D to the overriding signals
PD6/AIN0/
OC0A/PCINT22
0
0
0
0
OC0A ENABLE
OC0A
PCINT22 • PCIE2
1
PCINT22 INPUT
AIN0 INPUT
PD5/T1/OC0B/
PCINT21
0
0
0
0
OC0B ENABLE
OC0B
PCINT21 • PCIE2
1
PCINT21 INPUT
T1 INPUT
–
PD4/XCK/
T0/PCINT20
0
0
0
0
UMSEL
XCK OUTPUT
PCINT20 • PCIE2
1
PCINT20 INPUT
XCK INPUT
T0 INPUT
–
91
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