ATTINY25-15MZ Atmel, ATTINY25-15MZ Datasheet - Page 100
ATTINY25-15MZ
Manufacturer Part Number
ATTINY25-15MZ
Description
MCU AVR 2K FLASH 15MHZ 20-QFN
Manufacturer
Atmel
Series
AVR® ATtinyr
Datasheet
1.ATTINY25-15MZ.pdf
(196 pages)
Specifications of ATTINY25-15MZ
Package / Case
20-QFN
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Operating Temperature
-40°C ~ 125°C
Speed
16MHz
Number Of I /o
6
Eeprom Size
128 x 8
Core Processor
AVR
Program Memory Type
FLASH
Ram Size
128 x 8
Program Memory Size
2KB (2K x 8)
Data Converters
A/D 4x10b
Oscillator Type
Internal
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Connectivity
USI
Core Size
8-Bit
Processor Series
ATTINY2x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
128 B
Interface Type
UART, SPI, USI
Maximum Clock Frequency
16 MHz
Number Of Programmable I/os
6
Number Of Timers
2
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 4 Channel
Data Rom Size
128 B
A/d Bit Size
10 bit
A/d Channels Available
4
Height
0.75 mm
Length
4 mm
Supply Voltage (max)
5.5 V
Supply Voltage (min)
2.7 V
Width
4 mm
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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16.2.3
16.2.4
100
ATtiny25/45/85
SPI Slave Operation Example
Two-wire Mode
The following code demonstrates how to use the USI module as a SPI Slave:
The code is size optimized using only eight instructions (+ ret). The code example assumes that
the DO is configured as output and USCK pin is configured as input in the DDR Register. The
value stored in register r16 prior to the function is called is transferred to the master device, and
when the transfer is completed the data received from the Master is stored back into the r16
Register.
Note that the first two instructions is for initialization only and needs only to be executed
once.These instructions sets Three-wire mode and positive edge Shift Register clock. The loop
is repeated until the USI Counter Overflow Flag is set.
The USI Two-wire mode is compliant to the Inter IC (TWI) bus protocol, but without slew rate lim-
iting on outputs and input noise filtering. Pin names used by this mode are SCL and SDA.
init:
...
SlaveSPITransfer:
SlaveSPITransfer_loop:
ldi
sts
sts
ldi
sts
lds
sbrs
rjmp
lds
ret
r16,(1<<USIWM0)|(1<<USICS1)
USICR,r16
USIDR,r16
r16,(1<<USIOIF)
USISR,r16
r16, USISR
r16, USIOIF
SlaveSPITransfer_loop
r16,USIDR
7598H–AVR–07/09
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