PIC18F1220-E/SS Microchip Technology, PIC18F1220-E/SS Datasheet - Page 27

IC MCU FLASH 2KX16 EEPROM 20SSOP

PIC18F1220-E/SS

Manufacturer Part Number
PIC18F1220-E/SS
Description
IC MCU FLASH 2KX16 EEPROM 20SSOP
Manufacturer
Microchip Technology
Series
PIC® 18Fr

Specifications of PIC18F1220-E/SS

Core Size
8-Bit
Program Memory Size
4KB (2K x 16)
Core Processor
PIC
Speed
40MHz
Connectivity
UART/USART
Peripherals
Brown-out Detect/Reset, LVD, POR, PWM, WDT
Number Of I /o
16
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4.2 V ~ 5.5 V
Data Converters
A/D 7x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 125°C
Package / Case
20-SSOP
Controller Family/series
PIC18
No. Of I/o's
16
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
40MHz
No. Of Timers
4
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
16
Number Of Timers
1 x 16 bit
Operating Supply Voltage
2 V to 5.5 V
Maximum Operating Temperature
+ 125 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 7 Channel
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
TABLE 5-3:
© 2009 Microchip Technology Inc.
WDTEN
HPOL
LPOL
PWMPIN
MCLRE
T1OSCMX
FLTAMX
BKBUG
XINST
BBSIZ<1:0>
STVREN
CP1
Note 1:
Bit Name
The BBSIZ<1:0> bits can not be changed once any of the following code-protect bits are enabled: CPB or
CP0, WRTB or WRT0, EBTRB or EBTR0.
(1)
PIC18F1230/1330 BIT DESCRIPTIONS (CONTINUED)
Configuration
CONFIG2H
CONFIG3H
CONFIG3H
CONFIG3H
CONFIG3L
CONFIG3L
CONFIG3L
CONFIG4L
CONFIG4L
CONFIG4L
CONFIG4L
CONFIG5L
Words
Watchdog Timer Enable bit
1 = WDT enabled
0 = WDT disabled (control is placed on SWDTEN bit)
High Side Transistors Polarity bit (Odd PWM Output Polarity Control bit)
1 = PWM 1, 3 and 5 are active-high (default)
0 = PWM 1, 3 and 5 are active-low
Low Side Transistors Polarity bit (Even PWM Output Polarity Control bit)
1 = PWM 0, 2 and 4 are active-high (default)
0 = PWM 0, 2 and 4 are active-low
PWM Output Pins Reset State Control bit
1 = PWM outputs disabled upon Reset
0 = PWM outputs drive active states upon Reset
MCLR Pin Enable bit
1 = MCLR pin enabled, RA5 input pin disabled
0 = RA5 input pin enabled, MCLR pin disabled
T1OSC MUX bit
1 = T1OSC pins reside on RA6 and RA7
0 = T1OSC pins reside on RB2 and RB3
FLTA MUX bit
1 = FLTA is multiplexed with RA5
0 = FLTA is multiplexed with RA7
Background Debugger Enable bit
1 = Background debugger disabled, RB6 and RB7 configured as general
0 = Background debugger enabled, RB6 and RB7 are dedicated to In-Circuit
Extended Instruction Set Enable bit
1 = Instruction set extension and Indexed Addressing mode enabled
0 = Instruction set extension and Indexed Addressing mode disabled
For PIC18F1330 device:
11 = 1 kW Boot Block size
10 = 1 kW Boot Block size
01 = 512W Boot Block size
00 = 256W Boot Block size
For PIC18F1230 device:
11 = 512W Boot Block size
10 = 512W Boot Block size
01 = 512W Boot Block size
00 = 256W Boot Block size
Stack Overflow/Underflow Reset Enable bit
1 = Reset on stack overflow/underflow enabled
0 = Reset on stack overflow/underflow disabled
Code Protection bits (Block 1 code memory area)
1 = Block 1 is not code-protected
0 = Block 1 is code-protected
Boot Block Size Select bits
purpose I/O pins
Debug
(Legacy mode)
Description
PIC18F1230/1330
DS39752B-page 27

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