ATMEGA48A-AU Atmel, ATMEGA48A-AU Datasheet - Page 252
![IC MCU AVR 4K FLASH 32TQFP](/photos/6/91/69154/313-32-tqfp_sml.jpg)
ATMEGA48A-AU
Manufacturer Part Number
ATMEGA48A-AU
Description
IC MCU AVR 4K FLASH 32TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA48A-AU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
512 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-TQFP, 32-VQFP
Controller Family/series
Atmega
No. Of I/o's
23
Eeprom Memory Size
256Byte
Ram Memory Size
512Byte
Cpu Speed
20MHz
Rohs Compliant
Yes
Processor Series
ATmega
Core
AVR
Data Bus Width
8 bit
Data Ram Size
512 B
Interface Type
TWI, SPI, USART
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
23
Number Of Timers
3
Operating Supply Voltage
3.3 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
Operating Temperature Range
- 40 C to + 85 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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8271C–AVR–08/10
Figure 23-1. Analog to Digital Converter Block Schematic Operation,
The analog input channel is selected by writing to the MUX bits in ADMUX. Any of the ADC input
pins, as well as GND and a fixed bandgap voltage reference, can be selected as single ended
inputs to the ADC. The ADC is enabled by setting the ADC Enable bit, ADEN in ADCSRA. Volt-
age reference and input channel selections will not go into effect until ADEN is set. The ADC
does not consume power when ADEN is cleared, so it is recommended to switch off the ADC
before entering power saving sleep modes.
The ADC generates a 10-bit result which is presented in the ADC Data Registers, ADCH and
ADCL. By default, the result is presented right adjusted, but can optionally be presented left
adjusted by setting the ADLAR bit in ADMUX.
If the result is left adjusted and no more than 8-bit precision is required, it is sufficient to read
ADCH. Otherwise, ADCL must be read first, then ADCH, to ensure that the content of the Data
Registers belongs to the same conversion. Once ADCL is read, ADC access to Data Registers
is blocked. This means that if ADCL has been read, and a conversion completes before ADCH is
ATmega48A/48PA/88A/88PA/168A/168PA/328/328
AREF
ADC7
ADC6
ADC5
ADC4
ADC3
ADC2
ADC1
ADC0
AVCC
GND
TEMPERATURE
INTERNAL 1.1V
REFERENCE
REFERENCE
BANDGAP
SENSOR
8-BIT DATA BUS
INPUT
MUX
ADC MULTIPLEXER
SELECT (ADMUX)
MUX DECODER
10-BIT DAC
ADC CTRL. & STATUS
REGISTER (ADCSRA)
ADC CONVERSION
COMPLETE IRQ
CONVERSION LOGIC
PRESCALER
SAMPLE & HOLD
COMPARATOR
15
+
-
ADC DATA REGISTER
(ADCH/ADCL)
ADC MULTIPLEXER
OUTPUT
0
252
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