PIC18F45J10-I/PT Microchip Technology, PIC18F45J10-I/PT Datasheet - Page 3

• Manufacturer Part Number: PIC18F45J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

Silicon Errata Issues
1. Module: Timer1
2. Module: EUSART
3. Module: EUSART
 2009 Microchip Technology Inc.
Note:
In 16-Bit Asynchronous Counter mode or 16-Bit
Asynchronous Oscillator mode, the TMR1H buf-
fer does not update when TMR1L is read. This
issue only affects the reading of the TMR1H reg-
isters. The timers increment and set the interrupt
flags as expected. The Timer registers can also
be written as expected.
Work around
Use the 8-bit mode by clearing the RD16
(T1CON<7>) bit or use the synchronization
option by clearing, T1SYNC (T1CON<2>).
Affected Silicon Revisions
In asynchronous duplex communication, the
reception can get corrupted if any bit of the
TXSTA register is modified during a reception.
Work around
The CSRC (TXSTA<7>) bit should not be set.
Though this is a “don’t care” bit in Asynchronous
mode, make sure that this bit is not set.
Affected Silicon Revisions
In Synchronous mode, EUSART baud rates
using SPBRG values of ‘0’ and ‘1’ may not
function correctly.
Work around
Use another baud rate configuration to generate
the desired baud rate.
Affected Silicon Revisions
A2
A2
A2
X
X
X
This document summarizes all silicon
errata issues from all revisions of silicon,
previous as well as current. Only the
issues indicated by the shaded column in
the following tables apply to the current
silicon revision (A4).
A3
A3
A3
X
X
X
A4
A4
A4
X
X
X
PIC18F45J10 FAMILY
4. Module: EUSART
5. Module: EUSART
After the last received byte has been read from
the EUSART Receive Buffer (RCREG), the
value is no longer valid for subsequent read
operations. The RCREG register should only be
read once for each byte received.
Work around
After each byte is received from the EUSART,
store the byte into a user variable. To determine
when a byte is available to read from RCREG,
poll the RCIDL bit (BAUDCON<6>) for a low-to-
high transition, or use the EUSART Receive
Interrupt Flag (RCIF, PIR1<5>).
Affected Silicon Revisions
In 9-Bit Asynchronous Full-Duplex Receive
mode, received data may be corrupted if the
TX9D
immediately after RCIDL (BAUDCON<6>) is
set.
Work around
Only write to TX9D when a reception is not in
progress (RCIDL = 1). No interrupt is associated
with RCIDL, therefore, it must be polled in
software to determine when TX9D can be
updated.
Affected Silicon Revisions
A2
A2
X
X
A3
A3
bit
X
X
(TXSTA<0>)
A4
A4
X
X
is
DS80494B-page 3
not
modified