PIC18F45J10-I/PT Microchip Technology, PIC18F45J10-I/PT Datasheet - Page 4

• Manufacturer Part Number: PIC18F45J10-I/PT
• Description: IC PIC MCU FLASH 16KX16 44TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F45J10-I/PT

• Core Size: 8-Bit
• Program Memory Size: 32KB (16K x 16)
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: I²C, SPI, UART/USART
• Number Of I /o: 32
• Program Memory Type: FLASH
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 44-TQFP, 44-VQFP
• Controller Family/series: PIC18
• No. Of I/o's: 32
• Ram Memory Size: 1KB
• Cpu Speed: 40MHz
• No. Of Timers: 3
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 1024 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Maximum Operating Temperature: + 100 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DV164136, DM163022, DM183040
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 13 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC162074 - HEADER INTRFC MPLAB ICD2 44TQFPMA180013 - MODULE PLUG-IN 18F45J10 44TQFPAC162067 - HEADER INTRFC MPLAB ICD2 40/28PAC164330 - MODULE SKT FOR 44TQFP 18F45J10
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details

PIC18F45J10 FAMILY
6. Module: MSSP
7. Module: MSSP (I
DS80494B-page 4
In SPI mode, the Buffer Full flag bit (BF,
SSPxSTAT<0>), the Write Collision Detect bit
(WCOL, SSPxCON1<7>) and the Receive Over-
flow Indicator bit (SSPOV, SSPxCON1<6>) are
not reset upon disabling the SPI module (by
clearing the SSPEN bit in the SSPxCON1
register).
For example, if SSPxBUF is full (BF bit is set)
and the MSSP module is disabled and re-
enabled, the BF bit will remain set. In SPI Slave
mode, a subsequent write to SSPxBUF will
result in a write collision. Also, if a new byte is
received, a receive overflow will occur.
Work around
Ensure that if the buffer is full, SSPxBUF is read
(thus, clearing the BF flag) and WCOL is clear
before disabling the MSSP module. If the
module is configured in SPI Slave mode, ensure
that the SSPOV bit is clear before disabling the
module.
Affected Silicon Revisions
After a Power-on Reset, the I
initialize properly by just configuring the SCLx
and SDAx pins as either inputs or outputs. This
has only been seen in a few unique system
environments.
A test of a statistically significant sample of pre-
production systems, across the voltage and
current range of the application’s power supply,
should indicate if a system is susceptible to this
issue.
Work around
Before configuring the module for I
1. Configure the SCLx and SDAx pins as outputs
2. Force SCLx and SDAx low by clearing the
3. While keeping the LAT bits clear, configure
Once this is done, use the SSPxCON1 and
SSPxCON2 registers to configure the proper
I
Affected Silicon Revisions
2
A2
C mode as before.
A2
X
X
by clearing their corresponding TRIS bits.
corresponding LAT bits.
SCLx and SDAx as inputs by setting their TRIS
bits.
A3
A3
X
X
A4
A4
X
X
2
C™ Mode)
2
C mode may not
2
C operation:
8. Module: Core (Program Memory Space)
1.
2.
Writes to program memory address, 300000h,
that are not blocked, can cause the program
memory at different locations to be corrupted.
Work around
Do not write to address, 300000h.
If you wish to modify the contents of the
Configuration registers:
Modify the Configuration Words located at the
end of the user memory:
• For PIC18FX5J10 devices – 7FF4h
• For PIC18FX4J10 devices – 3FF4h
Issue a Reset command.
This will reload the Configuration registers with
the new configuration setting.
Affected Silicon Revisions
A2
X
A3
X
A4
X
 2009 Microchip Technology Inc.