ATMEGA16A-MUR Atmel, ATMEGA16A-MUR Datasheet - Page 223
ATMEGA16A-MUR
Manufacturer Part Number
ATMEGA16A-MUR
Description
MCU AVR 16KB FLASH 16MHZ 44QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheet
1.ATMEGA16A-MU.pdf
(352 pages)
Specifications of ATMEGA16A-MUR
Core Processor
AVR
Core Size
8-Bit
Speed
16MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
32
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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22.9.2
8154B–AVR–07/09
ADCSRA – ADC Control and Status Register A
Table 22-4.
Note:
• Bit 7 – ADEN: ADC Enable
Writing this bit to one enables the ADC. By writing it to zero, the ADC is turned off. Turning the
ADC off while a conversion is in progress, will terminate this conversion.
• Bit 6 – ADSC: ADC Start Conversion
In Single Conversion mode, write this bit to one to start each conversion. In Free Running Mode,
write this bit to one to start the first conversion. The first conversion after ADSC has been written
after the ADC has been enabled, or if ADSC is written at the same time as the ADC is enabled,
will take 25 ADC clock cycles instead of the normal 13. This first conversion performs initializa-
tion of the ADC.
ADSC will read as one as long as a conversion is in progress. When the conversion is complete,
it returns to zero. Writing zero to this bit has no effect.
• Bit 5 – ADATE: ADC Auto Trigger Enable
When this bit is written to one, Auto Triggering of the ADC is enabled. The ADC will start a con-
version on a positive edge of the selected trigger signal. The trigger source is selected by setting
the ADC Trigger Select bits, ADTS in SFIOR.
• Bit 4 – ADIF: ADC Interrupt Flag
This bit is set when an ADC conversion completes and the Data Registers are updated. The
ADC Conversion Complete Interrupt is executed if the ADIE bit and the I-bit in SREG are set.
ADIF is cleared by hardware when executing the corresponding interrupt handling vector. Alter-
natively, ADIF is cleared by writing a logical one to the flag. Beware that if doing a Read-Modify-
Write on ADCSRA, a pending interrupt can be disabled. This also applies if the SBI and CBI
instructions are used.
• Bit 3 – ADIE: ADC Interrupt Enable
When this bit is written to one and the I-bit in SREG is set, the ADC Conversion Complete Inter-
rupt is activated.
Bit
Read/Write
Initial Value
MUX4:0
11101
11110
11111
1. The differential input channels are not tested for devices in PDIP Package. This feature is only
guaranteed to work for devices in TQFP and QFN/MLF Packages
Single Ended
Input
1.22 V (V
0 V (GND)
Input Channel and Gain Selections (Continued)
ADEN
R/W
7
0
BG
)
ADSC
R/W
6
0
ADATE
Positive Differential
Input
ADC5
N/A
R/W
5
0
ADIF
R/W
4
0
ADIE
R/W
3
0
ADPS2
Negative Differential Input
ADC2
R/W
2
0
ADPS1
R/W
1
0
ATmega16A
ADPS0
R/W
0
0
ADCSRA
Gain
1x
223
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