PIC18F1320-E/SS Microchip Technology, PIC18F1320-E/SS Datasheet - Page 224

• Manufacturer Part Number: PIC18F1320-E/SS
• Description: IC MCU FLASH 4KX16 EEPROM 20SSOP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F1320-E/SS

• Program Memory Type: FLASH
• Program Memory Size: 8KB (4K x 16)
• Package / Case: 20-SSOP
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 40MHz
• Connectivity: UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 16
• Eeprom Size: 256 x 8
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 7x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 16
• Number Of Timers: 1 x 16 bit
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DM163014, DV164136
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 7 bit
• Package: 20SSOP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

PIC18F1220/1320
RETFIE
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
DS39605F-page 222
Q Cycle Activity:
After Interrupt
operation
Decode
PC
W
BSR
Status
GIE/GIEH, PEIE/GIEL
Q1
No
operation
operation
Return from Interrupt
[ label ]
s ∈ [0,1]
(TOS) → PC,
1 → GIE/GIEH or PEIE/GIEL,
if s = 1
(WS) → W,
(STATUSS) → Status,
(BSRS) → BSR,
PCLATU, PCLATH are unchanged.
GIE/GIEH, PEIE/GIEL.
Return from interrupt. Stack is
popped and Top-of-Stack (TOS) is
loaded into the PC. Interrupts are
enabled by setting either the high
or low priority global interrupt
enable bit. If ‘s’ = 1, the contents of
the shadow registers, WS,
STATUSS and BSRS, are loaded
into their corresponding registers,
W, Status and BSR. If ‘s’ = 0, no
update of these registers occurs
(default).
1
2
RETFIE
0000
Q2
No
No
1
RETFIE [s]
0000
operation
operation
=
=
=
=
=
Q3
No
No
TOS
WS
BSRS
STATUSS
1
0001
Set GIEH or
from stack
operation
Pop PC
GIEL
Q4
No
000s
RETLW
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Example:
TABLE
Q Cycle Activity:
:
:
:
CALL TABLE ; W contains table
ADDWF PCL
RETLW k0
RETLW k1
RETLW kn
Before Instruction
After Instruction
operation
Decode
W
W
Q1
No
; offset value
; W now has
; table value
; W = offset
; Begin table
;
; End of table
=
=
operation
Return Literal to W
[ label ]
0 ≤ k ≤ 255
k → W,
(TOS) → PC,
PCLATU, PCLATH are unchanged
None
W is loaded with the eight-bit literal
‘k’. The program counter is loaded
from the top of the stack (the return
address). The high address latch
(PCLATH) remains unchanged.
1
2
literal ‘k’
Read
0000
Q2
No
0x07
value of kn
© 2007 Microchip Technology Inc.
RETLW k
1100
operation
Process
Data
Q3
No
kkkk
from stack,
Write to W
operation
Pop PC
Q4
No
kkkk