ATMEGA168P-20MQ Atmel, ATMEGA168P-20MQ Datasheet - Page 94
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ATMEGA168P-20MQ
Manufacturer Part Number
ATMEGA168P-20MQ
Description
MCU AVR 16K FLASH 20MHZ 32-QFN
Manufacturer
Atmel
Series
AVR® ATmegar
Specifications of ATMEGA168P-20MQ
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
23
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
32-VQFN Exposed Pad, 32-HVQFN, 32-SQFN, 32-DHVQFN
For Use With
ATSTK600-TQFP32 - STK600 SOCKET/ADAPTER 32-TQFPATAVRDRAGON - KIT DRAGON 32KB FLASH MEM AVR
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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14.3
14.4
8025L–AVR–7/10
Timer/Counter Clock Sources
Counter Unit
The Timer/Counter can be clocked internally, via the prescaler, or by an external clock source on
the T0 pin. The Clock Select logic block controls which clock source and edge the Timer/Counter
uses to increment (or decrement) its value. The Timer/Counter is inactive when no clock source
is selected. The output from the Clock Select logic is referred to as the timer clock (clk
The double buffered Output Compare Registers (OCR0A and OCR0B) are compared with the
Timer/Counter value at all times. The result of the compare can be used by the Waveform Gen-
erator to generate a PWM or variable frequency output on the Output Compare pins (OC0A and
OC0B).
Compare Flag (OCF0A or OCF0B) which can be used to generate an Output Compare interrupt
request.
The Timer/Counter can be clocked by an internal or an external clock source. The clock source
is selected by the Clock Select logic which is controlled by the Clock Select (CS02:0) bits
located in the Timer/Counter Control Register (TCCR0B). For details on clock sources and pres-
caler, see
The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit.
14-2
Figure 14-2. Counter Unit Block Diagram
Signal description (internal signals):
Depending of the mode of operation used, the counter is cleared, incremented, or decremented
at each timer clock (clk
selected by the Clock Select bits (CS02:0). When no clock source is selected (CS02:0 = 0) the
timer is stopped. However, the TCNT0 value can be accessed by the CPU, regardless of
whether clk
count operations.
shows a block diagram of the counter and its surroundings.
count
direction
clear
clk
top
bottom
See Section “15.7.3” on page 121.
Tn
”Timer/Counter0 and Timer/Counter1 Prescalers” on page
T0
is present or not. A CPU write overrides (has priority over) all counter clear or
DATA BUS
TCNTn
T0
). clk
Increment or decrement TCNT0 by 1.
Select between increment and decrement.
Clear TCNT0 (set all bits to zero).
Timer/Counter clock, referred to as clk
Signalize that TCNT0 has reached maximum value.
Signalize that TCNT0 has reached minimum value (zero).
T0
can be generated from an external or internal clock source,
direction
count
clear
bottom
for details. The compare match event will also set the
Control Logic
top
ATmega48P/88P/168P
TOVn
(Int.Req.)
clk
Tn
Clock Select
( From Prescaler )
Detector
Edge
T0
139.
in the following.
Tn
T0
).
Figure
94
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