ATTINY461A-SU Atmel, ATTINY461A-SU Datasheet - Page 63
![IC MCU AVR 4K FLASH 20MHZ 20SOIC](/photos/6/80/68042/453-20-soic_sml.jpg)
ATTINY461A-SU
Manufacturer Part Number
ATTINY461A-SU
Description
IC MCU AVR 4K FLASH 20MHZ 20SOIC
Manufacturer
Atmel
Series
AVR® ATtinyr
Specifications of ATTINY461A-SU
Core Processor
AVR
Core Size
8-Bit
Speed
20MHz
Connectivity
USI
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
16
Program Memory Size
4KB (2K x 16)
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 11x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-SOIC (7.5mm Width)
Controller Family/series
ATtiny
No. Of I/o's
16
Eeprom Memory Size
256Byte
Ram Memory Size
256Byte
Cpu Speed
20MHz
Rohs Compliant
Yes
Processor Series
ATTINY4x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
SPI
Maximum Clock Frequency
20 MHz
Number Of Programmable I/os
16
Operating Supply Voltage
1.8 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
EWAVR, EWAVR-BL
Development Tools By Supplier
ATAVRDRAGON, ATSTK500, ATSTK600, ATAVRISP2, ATAVRONEKIT
Minimum Operating Temperature
- 40 C
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ATTINY461A-SU
Manufacturer:
FSC
Quantity:
30 000
Part Number:
ATTINY461A-SU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Company:
Part Number:
ATTINY461A-SUR
Manufacturer:
HITTIE
Quantity:
2 140
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8197B–AVR–01/10
Table 10-4
shown in
Table 10-4.
Table 10-5.
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Signal
Name
PUOE
PUOV
DDOE
DDOV
PVOE
PVOV
PTOE
DIEOE
DIEOV
DI
AIO
Figure 10-5 on page
and
PA7/ADC6/AIN0/
PCINT7
0
0
0
0
0
0
0
PCINT7 • PCIE +
ADC6D
ADC6D
PCINT7
ADC6, AIN0
PA3/AREF/
PCINT3
0
0
0
0
0
0
0
PCINT3 •
PCIE
0
PCINT3
AREF
Overriding Signals for Alternate Functions in PA7:PA4
Overriding Signals for Alternate Functions in PA3:PA0
Table 10-5
PA2/ADC2/INT1/
USCK/SCL/PCINT2
0
0
USI_TWO_WIRE •
USIPOS
(USI_SCL_HOLD +
PORTB2) • DDB2 •
USIPOS
USI_TWO_WIRE •
DDRB2
0
USI_PTOE • USIPOS
PCINT2 • PCIE + INT1 +
ADC2D + USISIE •
USIPOS
ADC2D
USCK/SCL/INT1/ PCINT2
ADC2
relate the alternate functions of Port A to the overriding signals
59.
PA6/ADC5/AIN1/
PCINT6
0
0
0
0
0
0
0
PCINT6 • PCIE +
ADC5D
ADC5D
PCINT6
ADC5, AIN1
PA1/ADC1/DO/
PCINT1
0
0
0
0
USI_THREE_WI
RE • USIPOS
DO • USIPOS
0
PCINT1 • PCIE +
ADC1D
ADC1D
PCINT1
ADC1
PA5/ADC4/AIN2/
PCINT5
0
0
0
0
0
0
0
PCINT5 • PCIE +
ADC4D
ADC4D
PCINT5
ADC4, AIN2
PA0/ADC0/DI/SDA/
PCINT0
0
0
USI_TWO_WIRE •
USIPOS
(SDA + PORTB0) •
DDRB0 • USIPOS
USI_TWO_WIRE •
DDRB0 • USIPOS
0
0
PCINT0 • PCIE +
ADC0D + USISIE •
USIPOS
ADC0D
DI/SDA/PCINT0
ADC0
PA4/ADC3/ICP0/
PCINT4
0
0
0
0
0
0
0
PCINT4 • PCIE +
ADC3D
ADC3D
ICP0/PCINT4
ADC3
63
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