PIC18LF25K22-I/SS Microchip Technology, PIC18LF25K22-I/SS Datasheet - Page 208
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PIC18LF25K22-I/SS
Manufacturer Part Number
PIC18LF25K22-I/SS
Description
MCU 8BIT 32KB FLASH 3.6V 28SSOP
Manufacturer
Microchip Technology
Series
PIC® XLP™ 18Fr
Specifications of PIC18LF25K22-I/SS
Core Size
8-Bit
Program Memory Size
32KB (16K x 16)
Core Processor
PIC
Speed
64MHz
Connectivity
I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, HLVD, POR, PWM, WDT
Number Of I /o
24
Program Memory Type
FLASH
Eeprom Size
256 x 8
Ram Size
1.5K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Data Converters
A/D 19x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
28-SSOP
Controller Family/series
PIC18
No. Of I/o's
25
Eeprom Memory Size
256Byte
Ram Memory Size
1536Byte
Cpu Speed
64MHz
No. Of Timers
7
Processor Series
PIC18LF
Core
PIC
Data Bus Width
8 bit
Data Ram Size
1536 B
Interface Type
I2C, SPI, EUSART
Maximum Clock Frequency
64 MHz
Number Of Programmable I/os
25
Number Of Timers
7
Operating Supply Voltage
1.8 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164005
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 17 Channel
On-chip Dac
5 bit
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC18LF25K22-I/SS
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
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PIC18(L)F2X/4XK22
The I
features:
• Master mode
• Slave mode
• Byte NACKing (Slave mode)
• Limited Multi-master support
• 7-bit and 10-bit addressing
• Start and Stop interrupts
• Interrupt masking
• Clock stretching
• Bus collision detection
• General call address matching
• Address masking
• Address Hold and Data Hold modes
• Selectable SDAx hold times
Figure 15-2
module in Master mode.
I
FIGURE 15-2:
DS41412D-page 208
2
C interface module in Slave mode.
2
C interface supports the following modes and
SDAx
SCLx
is a block diagram of the I
MSSPx BLOCK DIAGRAM (I
Figure 15-3
SDAx in
SCLx in
Bus Collision
is a diagram of the
2
C interface
Read
MSb
Generate (SSPxCON2)
Address Match Detect
Write Collision Detect
Preliminary
end of XMIT/RCV
Start bit, Stop bit,
State Counter for
Clock Arbitration
Start bit Detect,
Stop bit Detect
Acknowledge
SSPxBUF
SSPxSR
2
C™ MASTER MODE)
The PIC18(L)F2X/4XK22 has two MSSP modules,
MSSP1 and MSSP2, each module operating indepen-
dently from the other.
LSb
Note 1: In devices with more than one MSSP
Write
Clock
Data Bus
Shift
Internal
2: Throughout
Set/Reset: S, P, SSPxSTAT, WCOL, SSPxOV
Reset SEN, PEN (SSPxCON2)
Set SSPxIF, BCLxIF
module, it is very important to pay close
attention to SSPxCONx register names.
SSP1CON1 and SSP1CON2 registers
control different operational aspects of
the same module, while SSP1CON1 and
SSP2CON1 control the same features for
two different modules.
references to an MSSP module in any of
its operating modes may be interpreted
as being equally applicable to MSSP1 or
MSSP2. Register names, module I/O
signals, and bit names may use the
generic designator ‘x’ to indicate the use
of a numeral to distinguish a particular
module when required.
2010 Microchip Technology Inc.
this
[SSPxM 3:0]
Baud Rate
Generator
(SSPxADD)
section,
generic
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